HS-82C85RH(2000) 查看數據表（PDF） - Intersil
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HS-82C85RH Datasheet PDF : 16 Pages
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HS-82C85RH
TABLE 3. CRYSTAL SPECIFICATIONS
PARAMETER
TYPICAL CRYSTAL SPECIFICATION
Frequency
2.4MHz to 15MHz
Type of Operation Parallel Resonant, Fund. Mode
Load Capacitance 20pF or 32pF
R Series (Max)
56Ω (f = 15MHz, CL = 32pF),
105Ω (f = 15MHz, CL = 20pF)
Frequency Source Selection
The F/C input is a strapping pin that selects either the crystal
oscillator or the EFI input as the source frequency for clock
generation. If the EFI input is selected as the source, the
oscillator section (OSC output) can be used independently
for another clock source. If a crystal is not used, then crystal
input X1 (pin 23) must be tied to VDD or GND and X2 (pin
22) should be left open. If the EFI mode is not used, then EFI
(pin 20) should be tied to VDD or GND.
Clock Generator
The clock generator consists of two synchronous divide-by-
three counters with special clear inputs that inhibit the
counting. One counter generates a 33% duty cycle
waveform (CLK) and the other generates a 50% duty cycle
waveform (CLK50). These two counters are negative-edge
synchronized, with the low-going transitions of both
waveforms occurring on the same oscillator transition. The
CLK and CLK50 output frequencies are one-third of the base
input frequency when SLO/FST is high and are equal to the
base input frequency divided by 768 when SLO/FST is low.
The CLK output is a 33% duty cycle clock signal designed to
drive the HS-80C86RH microprocessor directly. CLK50 has
a 50% duty cycle output synchronous with CLK, designed to
drive coprocessors and peripherals requiring a 50% duty
cycle clock.
PCLK is a peripheral clock signal with an output frequency
equal to the oscillator or EFI frequency divided by 6. PCLK
has a 50% duty cycle. PCLK is unaffected by SLO/FST. When
the HS-82C85RH is placed in the STOP mode, PCLK will
remain in its current state (logic high or logic low) until a RES
or START command restarts the HS-82C85RH clock circuitry.
PCLK is negative-edge synchronized with CLK and CLK50.
Since PCLK continues to run at the same frequency regardless
of the state of the SLO/FST pin, it can be used by other devices
in the system which need a fixed high frequency clock. For
example, PCLK could be used to clock an HS-82C54RH
programmable interval timer to produce a real-time clock for the
system or as a baud rate generator to maintain serial data
communications during SLOW mode operation.
Clock Synchronization
The clock synchronization (CSYNC) input allows the output
clocks to be synchronized with an external event (such as
another HS-82C85RH clock signal). CSYNC going active
causes all clocks (CLK, CLK50 and PCLK) to stop in the
HIGH state.
It is necessary to synchronize the CSYNC input to the EFI
clock using two flip-flops as shown in Figure 23. Multiple
external flip-flops are necessary to minimize the occurrence
of metastable (or indeterminate) states.
Ready Synchronization
Two RDY inputs (RDY1, RDY2) are provided to
accommodate two system buses. Each RDY input is
qualified by its corresponding AEN input (AEN1, AEN2).
Reception of a valid RDY signal causes the HS-82C85RH to
output READY high, informing the HS-80C86RH that the
pending data transfer may be concluded (see HS-80C86RH
data sheet system timing).
Synchronization is required for all asynchronous active-
going edges of either RDY input to guarantee that the RDY
set up and hold times are met. Inactive-going edges of RDY
in normally ready systems do not require synchronization
but must satisfy RDY setup and hold as a matter of proper
system design.
The ASYNC input defines two modes of RDY
synchronization operation. When ASYNC is LOW, two
stages of synchronization are provided for active RDY input
signals. Positive-going asynchronous RDY inputs will first be
synchronized to flip-flop one at the rising edge of CLK
(requiring a setup time TR1VCH) and then synchronized to
flip-flop two at the next falling edge of CLK, after which time
the READY output will go HIGH.
Negative-going asynchronous RDY inputs will be
synchronized directly to flip-flop two at the falling edge of
CLK, after which time the RDY output will go inactive. This
mode of operation is intended for use by asynchronous
(normally not ready) devices in the system which cannot be
guaranteed by design to meet the required RDY setup timing
(TR1VCL) on each bus cycle.
When ASYNC is high or left open, the first RDY flip-flop is
bypassed in the RDY synchronization logic. RDY inputs are
synchronized by flip-flop two on the falling edge of CLK
before they are presented to the processor. This mode is
available for synchronous devices that can be guaranteed to
meet the required RDY setup time. ASYNC can be changed
on every bus cycle to select the appropriate mode of
synchronization for each device in the system.
CSYNC WITH HS-82C85RH(s)
EFI
CLK
SYNCH
EFI
DQ
>
D
Q
>
HS-82C85RH
CSYNC
(TO OTHER
HS-82C85RHs)
FIGURE 23. CSYNC SYNCHRONIZATION METHODS
15
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