IS62LV12816ALL-70B 查看數據表（PDF） - Integrated Silicon Solution

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IS62LV12816ALL-70B

128K x 16 CMOS STATIC RAM

Integrated Silicon Solution 

IS62LV12816ALL

AC WAVEFORMS

READ CYCLE NO. 2(1,3) (CS, OE, AND UB/LB Controlled)

ADDRESS

OE

tRC

tAA

CE

LB, UB

DOUT

tLZCE

tLZB

HIGH-Z

tDOE

tLZOE

tACE

tBA

DATA VALID

tOHA

tHZOE

tHZCE

tHZB

Notes:

1. WE is HIGH for a Read Cycle.

2. The device is continuously selected. OE, CE, UB, or LB = VIL.

3. Address is valid prior to or coincident with CE LOW transition.

ISSI ®

WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)

Symbol Parameter

-55

-70

-100

Min. Max.

Min. Max.

Min. Max.

Unit

tWC

Write Cycle Time

55

—

70

—

100 —

ns

tSCE

CE to Write End

50

—

65

—

80

—

ns

tAW

Address Setup Time to Write End

50

—

65

—

80

—

ns

tHA

Address Hold from Write End

0

—

0

—

0

—

ns

tSA

Address Setup Time

0

—

0

—

0

—

ns

tPWB

LB, UB Valid to End of Write

45

—

60

—

80

—

ns

tPWE

WE Pulse Width

45

—

60

—

80

—

ns

tSD

Data Setup to Write End

25

—

30

—

40

—

ns

tHD

Data Hold from Write End

0

—

0

—

0

—

ns

tHZWE(3) WE LOW to High-Z Output

— 30

— 30

— 40

ns

tLZWE(3) WE HIGH to Low-Z Output

5

—

5

—

5

—

ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to

2.2V and output loading specified in Figure 1.

2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states

to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to

the rising or falling edge of the signal that terminates the write.

3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

6

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

04/17/01

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