RF133 查看數據表（PDF） - Conexant Systems

零件编号

产品描述 (功能)

比赛名单

RF133

RF/IF Transceiver For GSM Applications

Conexant Systems 

RF/IF Transceiver

RF133

TDMA slots

Rx slot

RXENA

T/H

T1

T2

T3

Front-end

enable

(external to RF133)

T4

C064

Figure 4. RF133 Sample and Hold Timing Diagram

Table 2. Minimum Required DC Offset Calibration Time T2 and Droop Rate

Hold Capacitor (CTH1, CTH2)

Cold start

Frame-to-frame

Typical droop-rate (@ I/Q outputs)

22 nF

60 µsec

10 µsec

1 mV/msec

120 nF

350 µs

60 µs

0.17 mV/ms

Because of on-chip loading currents, the hold capacitors (CTH1

and CTH2) slowly discharge causing the I and Q DC offset

voltages to droop if the RF133 remains uncalibrated for an

extended period of time (the droop rate versus the hold

capacitor is also shown in Table 2).

To rectify this voltage droop, it is recommended that

recalibration occur before every receive slot (i.e., every 4.6 ms

for GSM).

Internal Voltage Controlled Oscillator (VCO) and Frequency

Dividers. The differential VCO output is buffered and then fed to

three frequency dividers (Rx, Tx, PLL) with a selectable divide

ratio of either 2 or 4. The Rx and Tx dividers are both

quadrature dividers, which generate in-phase and quadrature

LOs. The buffered PLL divider output can be used to drive an

external PLL IC. The resonant element of the VCO is connected

to pins 28 (RES1) and 29 (RES2). Figure 5 shows the VCO

configuration.

Transmit Path_______________________________________

The transmit path consists of the following functional blocks:

• An I/Q modulator with IF output amplifier.

• A translation loop circuit consisting of a phase/frequency

detector, a charge pump, a Tx RF input buffer, an LO input

buffer, a mixer, two dividers, and a low pass filter.

The inputs to the I/Q modulator are differential I and Q

baseband signals which are low-pass filtered and then applied

to a pair of double balanced mixers (see Figure 2). The outputs

of the mixers are combined to produce a modulated signal

which is then filtered externally and input through pins 6 and 7

(TXIFIN+ and TXIFIN-) to the reference divider in the translation

loop.

The translation loop circuit together with the external transmit

VCO, external LO, and loop filter, form a PLL with a mixer in the

feedback loop. This PLL upconverts the modulated IF signal to

the transmit frequency which then drives the final power

amplifier. Since inherent bandpass filtering occurs in the PLL,

the need for a post PA duplexer is removed. This is the major

advantage a translation loop approach has over the

conventional upconversion scheme. The elimination of this

duplexer reduces the loss in the transmit path which in turn

reduces the output level of the final power amplifier and,

therefore, reduces the current consumption. Immediate benefits

of this approach are increased handset talk time and standby

time, and less component count.

100776A

Conexant

Proprietary Information and Specifications are Subject to Change

5

October 8, 1999

Share Link: