MP8831 查看數據表（PDF） - Exar Corporation
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MP8831 Datasheet PDF : 16 Pages
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MP8831
DC ELECTRICAL CHARACTERISTICS (CONT’D)
Symbol Parameter
Gain DAC (Cont’d)
VGFS Effective Full Scale Voltage
MGC
Maximum Change per
Conversion
Min.
ts-od Settling Time
Digital Characteristics
VIH
Digital Input High Voltage
3.5
VIL
Digital Input Low Voltage
VOH
Digital Output High Voltage
4.5
VOL
Digital Output Low Voltage
IOZ
High-Z Leakage
Digital Timing Specifications (Convert Mode)
tDV
Data Valid Delay (Rising Edge
CLK-A to AD[9:0]
New Data Valid
tSET1
DAbus Setup Time 1
40
tSET2
DAbus Setup Time 2
40
tHOLD1 DAbus Hold Time 1
tHOLD2 DAbus Hold Time 2
t1
Clock Timing
100
t2
Clock Timing
200
t3
Clock Timing
100
t4
Clock Timing
200
Typ. Max. Unit
Conditions
VOFS
2.82
20
300
V
% FS
ns
Measured at top of ADC reference
ladder through a switch.
Offset DAC = ZS
After specified change in DAC set-
ting, the ADC should output the
same code ± 1 LSB, assuming ana-
log input is constant.
Not Tested. Guaranteed by design.
V
1.5
V
V While sourcing 2mA.
0.5
V While sinking 2mA.
10
µA When inputs are idle or reading
DAC data.
30
50
0
0
200
200 25,000
200 25,000
200 25,000
ns With 30 pF load on each pin.
AD[9:0]
ns DA[7:0] to rising edge CLK-B.
ns DA[7:0] to rising edge CLK-A.
ns Rising edge CLK-B to DA[7:0].
ns Rising edge CLK-A to DA[7:0].
ns Rising edge CLK-B to falling edge
CLK-A.
ns Negative pulse width CLK-A.
ns Rising edge CLK-A to falling edge
CLK-B.
ns Negative pulse width CLK-B.
Rev. 1.00
5
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