EDI9LC644V 查看數據表（PDF） - White Electronic Designs => Micro Semi
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EDI9LC644V Datasheet PDF : 25 Pages
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EDI9LC644V
SDRAM CURRENT STATE TRUTH TABLE (CONT.)
Current State
Refreshing
Mode Register
Accessing
SDCE SDRAS SDCAS
L
L
L
L
L
L
L
L
H
L
L
H
L
H
L
L
H
L
L
H
H
L
H
H
H
X
X
L
L
L
L
L
L
L
L
H
L
L
H
L
H
L
L
H
L
L
H
H
L
H
H
H
X
X
Command
SDWE
L
A11
SDA 10-A 0
(BA)
OP Code
Description
Mode Register Set
Action
ILLEGAL
Notes
H
X
X
Auto or Self Refresh
ILLEGAL
L
X
X
Precharge
ILLEGAL
H
BA Row Address Bank Activate
ILLEGAL
L
BA
Column
Write
ILLEGAL
H
BA
Column
Read
ILLEGAL
L
X
X
Burst Termination
No Operation; Idle after tRC
H
X
X
No Operation
No Operation; Idle after tRC
X
X
X
Device Deselect
No Operation; Idle after tRC
L
OP Code
Mode Register Set
ILLEGAL
H
X
X
Auto or Self Refresh
ILLEGAL
L
X
X
Precharge
ILLEGAL
H
BA Row Address Bank Activate
ILLEGAL
L
BA
Column
Write
ILLEGAL
H
BA
Column
Read
ILLEGAL
L
X
X
Burst Termination
ILLEGAL
H
X
X
No Operation No Operation; Idle after two clock cycles
X
X
X
Device Deselect No Operation; Idle after two clock cycles
NOTES:
1. Both Banks must be idle otherwise it is an illegal action.
2. The Current State refers only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being referenced by the
Current State then the action may be legal depending on the state of that bank.
3. The minimum and maximum Active time (tRAS) must be satisfied.
4. The RAS to CAS Delay (tRCD) must occur before the command is given.
5. Address SDA10 is used to determine if the Auto Precharge function is activated.
6. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. The command is illegal if the minimum bank to bank
delay time (tRRD) is not satisfied.
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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