EDI9LC644V 查看數據表（PDF） - White Electronic Designs => Micro Semi

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EDI9LC644V

128Kx32 SSRAM/1Mx32 SDRAM

White Electronic Designs => Micro Semi 

EDI9LC644V

FIG. 14 SDRAM WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST

STOP @ BURST LENGTH = FULL PAGE

NOTES:

1. At full page mode, burst is end at the end of burst. So auto precharge is possible.

2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL.

BWE at write interrupt by precharge command is needed to prevent invalid write.

BWE should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge

cycle will be masked internally.

3. Burst stop is valid at every burst length.

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White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

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