ST16 查看數據表（PDF） - STMicroelectronics

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ST16

CHIP SET INTERFACE SPECIFICATION

STMicroelectronics 

FSD_CHIPSET_B/0104VP2

1.3.3 Write access chronogram

FPGA write access chronogram, for transmission FIFO or control register:

Figure 1 : FPGA write access chronogram

Mic_Ctrl_Data

Mic_RW

Mic_Strb_b

Mic_Data(7:0)

Rx_fifo_empty

Rx_irq_eof

Tx_start

Tx_fifo_empty

t1

t2

t3

t4

Control register writing

Data writing

ST16-19RFRDCS

In figure1, two types of access are shown. The first one is a Control register access (Mic_Ctrl_Data = ’1’)

and the second one is a FIFO access (Mic_Ctrl_Data = ’0’).

1.3.4 Read access chronogram

FPGA read access chronogram, for reception FIFO or status register:

Figure 2 FPGA read acces chronogram

Mic_Ctrl_Data

Mic_RW

Mic_Strb_b

Mic_Data(7:0)

Rx_fifo_empty

Rx_irq_eof

Tx_start

Tx_fifo_empty

t0 t1

t5

t3

t2

t6

t4

Acquisition of the first byte

Acquisition of the next bytes,

except the last one

In the figure 2, prior to sending data the FPGA takes the Rx_IRQ_EOF line low to indicate to the MCU that

the data can be recuperated.

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