STPCC0180BTC3 查看數據表（PDF） - STMicroelectronics

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STPCC0180BTC3

PC Compatible Embeded Microprocessor

STMicroelectronics 

PIN DESCRIPTION

Table 2-2. Definition of Signal Pins

Signal Name

Dir

Description

Qty

BASIC CLOCKS AND RESETS

SYSRSTI#

I System Reset / Power good

1

XTALI

I 14.3MHz Crystal Input

1

XTALO

I/O 14.3MHz Crystal Output - External Oscillator Input

1

HCLK

O Host Clock (Test)

1

DEV_CLK

O 24MHz Peripheral Clock (floppy drive)

1

GCLK2X

I/O 80MHz Graphics Clock

1

DCLK

I/O 135MHz Dot Clock

1

PCI_CLKI

I 33MHz PCI Input Clock

1

PCI_CLKO

O 33MHz PCI Output Clock (from internal PLL)

1

SYSRSTO#

O Reset Output to System

1

ISA_CLK

O ISA Clock Output - Multiplexer Select Line For IPC

1

ISA_CLK2X

O ISA Clock x 2 Output - Multiplexer Select Line For IPC

1

MEMORY INTERFACE

MA[11:0]

I/O Memory Address

12

RAS#[3:0]

O Row Address Strobe

4

CAS#[7:0]

O Column Address Strobe

8

MWE#

O Write Enable

1

MD[63:0]

I/O Memory Data

64

PCI INTERFACE

AD[31:0]

I/O PCI Address / Data

32

CBE[3:0]

I/O Bus Commands / Byte Enables

4

FRAME#

I/O Cycle Frame

1

TRDY#

I/O Target Ready

1

IRDY#

I/O Initiator Ready

1

STOP#

I/O Stop Transaction

1

DEVSEL#

I/O Device Select

1

PAR

I/O Parity Signal Transactions

1

SERR#

O System Error

1

LOCK#

I PCI Lock

1

PCIREQ#[2:0]

I PCI Request

3

PCIGNT #[2:0]

O PCI Grant

3

PCI_INT[3:0]

I PCI Interrupt Request

4

VDD5

I 5V Power Supply for PCI ESD protection

4

ISA AND IDE COMBINED ADDRESS/DATA

LA[23:22] / SCS3#,SCS1#

I/O Unlatched Address (ISA) / Secondary Chip Select (IDE)

2

LA[21:20] / PCS3#,PCS1#

I/O Unlatched Address (ISA) / Primary Chip Select (IDE)

2

LA[19:17] / DA[2:0]

O Unlatched Address (ISA) / Address (IDE)

3

RMRTCCS# / DD[15]

I/O ROM/RTC Chip Select / Data Bus bit 15 (IDE)

1

KBCS# / DD[14]

I/O Keyboard Chip Select / Data Bus bit 14 (IDE)

1

RTCRW# / DD[13]

I/O RTC Read/Write / Data Bus bit 13 (IDE)

1

RTCDS# / DD[12]

I/O RTC Data Strobe / Data Bus bit 12 (IDE)

1

SA[19:8] / DD[11:0]

I/O Latched Address (ISA) / Data Bus (IDE)

16

SA[7:0]

I/O Latched Address (IDE)

4

SD[15:0]

I/O Data Bus (ISA)

16

Issue 1.2

11/51

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