DS2141A 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS2141A

T1 Controller

Dallas Semiconductor -> Maxim Integrated 

DS2141A

2.0 PARALLEL PORT

The DS2141A is controlled via a multiplexed bidirectional

address/data bus by an external microcontroller or micro-

processor. The DS2141A can operate with either Intel or

Motorola bus timing configurations. If the BTS pin is tied

low, Intel timing will be selected; if tied high, Motorola tim-

ing will be selected. All Motorola bus signals are listed in

parenthesis (). See the timing diagrams in the AC Electri-

cal Characteristics for more details. The multiplexed bus

on the DS2141A saves pins because the address in-

formation and data information share the same signal

paths. The addresses are presented to the pins in the

first portion of the bus cycle and data will be transferred

on the pins during second portion of the bus cycle. Ad-

dresses must be valid prior to the falling edge of ALE(AS),

at which time the DS2141A latches the address from the

AD0 to AD7 pins. Valid write data must be present and

held stable during the later portion of the DS or WR

pulses. In a read cycle, the DS2141A outputs a byte of

data during the latter portion of the DS or RD pulses. The

read cycle is terminated and the bus returns to a high im-

pedance state as RD transitions high in Intel timing or as

DS transitions low in Motorola timing.

3.0 CONTROL REGISTERS

The operation of the DS2141A is configured via a set of

six registers. Typically, the control registers are only ac-

cessed when the system is first powered up. Once, the

DS2141A has been initialized, the control registers will

only need to be accessed when there is a change in the

system configuration. There are two Receive Control

Registers (RCR1 and RCR2), two Transmit Control

Registers (TCR1 and TCR2), and two Common Control

Registers (CCR1 and CCR2). Each of the six registers

is described below.

RCR1: RECEIVE CONTROL REGISTER 1 (2Bh)

(MSB)

–

ARC

OOF1

OOF2

SYNCC

SYNCT

SYNCE

(LSB)

RESYNC

SYMBOL

–

ARC

POSITION

RCR1.7

RCR1.6

OOF1

RCR1.5

OOF2

RCR1.4

SYNCC

RCR1.3

SYNCT

RCR1.2

SYNCE

RCR1.1

RESYNC

RCR1.0

NAME AND DESCRIPTION

Not Assigned. Should be set to 0 when written to.

Auto Resync Criteria.

0=Resync on OOF or RCL event.

1=Resync on OOF only.

Out Of Frame Select 1.

0=2/4 frame bits in error.

1=2/5 frame bits in error.

Out Of Frame Select 2.

0=follow RCR1.5.

1=2/6 frame bits in error.

Sync Criteria.

In D4 Framing Mode.

0=search for Ft pattern, then search for Fs pattern.

1=cross couple Ft and Fs pattern.

In ESF Framing Mode.

0=search for FPS pattern only.

1=search for FPS and verify with CRC6.

Sync Time.

0=qualify 10 bits.

1=qualify 24 bits.

Sync Enable.

0=auto resync enabled.

1=auto resync disabled.

Resync. When toggled from low to high, a resync is initiated. Must be

cleared and set again for a subsequent resync.

022698 6/35

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