TSDW
TCR2.4
TSM
TCR2.3
TSIO
TCR2.2
TD4YM
TCR2.1
B7ZS
TCR2.0
DS2141A
TSYNC Double–Wide.
0=do not pulse double–wide in signaling frames.
1=do pulse double–wide in signaling frames.
(note: this bit must be set to 0 when TCR2.3 = 1 or when TCR2.2 = 0).
TSYNC Mode Select.
0=frame mode (see the timing in Section 13).
1=multiframe mode (see the timing in Section 13).
TSYNC I/O Select.
0=TSYNC is an input.
1=TSYNC is an output.
Transmit Side D4 Yellow Alarm Select.
0=0s in bit 2 of all channels.
1=a 1 in the S–bit position of frame 12.
Bit 7 Zero Suppression Enable.
0=no stuffing occurs.
1=Bit 7 forced to a 1 in channels with all 0s.
CCR1: COMMON CONTROL REGISTER 1 (37h)
(MSB)
TESE
P34F
RSAO
–
SCLKM
RESE
PLB
SYMBOL
TESE
POSITION
CCR1.7
P34F
CCR1.6
RSAO
CCR1.5
–
SCLKM
CCR1.4
CCR1.3
RESE
CCR1.2
PLB
CCR1.1
LLB
CCR1.0
NAME AND DESCRIPTION
Transmit Elastic Store Enable.
0=elastic store is bypassed.
1=elastic store is enabled.
Function of Pin 34.
0=Receive Loss of Sync (RLOS).
1=Loss of Transmit Clock (LOTC).
Receive Signaling All 1’s.
0=allow robbed signaling bits to appear at RSER.
1=force all robbed signaling bits at RSER to 1.
Not Assigned. Should be set to 0 when written to.
SYSCLK Mode Select.
0=if SYSCLK is 1.544 MHz.
1=if SYSCLK is 2.048 MHz.
Receive Elastic Store Enable.
0=elastic store is bypassed.
1=elastic store is enabled.
Payload Loopback.
0=loopback disabled.
1=loopback enabled.
Local Loopback.
0=loopback disabled.
1=loopback enabled.
(LSB)
LLB
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