GDC21D401B 查看數據表（PDF） - Hyundai Micro Electronics

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GDC21D401B

Video Decoder

Hyundai Micro Electronics 

1. General Description

The Video Decoder(VD) decodes video

elementary stream of MPEG-2(ISO/ICE

13818-2)MP@HL. It supports the ATSC

digital TV video standard, and can be used for

the video part of the ATSC digital TV with the

Transport Decoder and the VDP(Video

Display Processor). Picture decoding timing

can be controlled internally for A/V lip

synchronization, and externally for Video

Trick Mode by host microprocessor via I2C bus.

The Video Decoder can extract video user data

including caption from video elementary

stream, and host microprocessor can read the

video user data from the Video Decoder(VD)

via I2C. It uses four 16x1M SDRAMs and can

support up to 81 MHz memory clock speed.

GGDDCC2211DD440011BB

Video Decoder

2. Features

• Supports MPEG-2 (ISO/ICE 13818-2)

MP@HL

• Supports all video input formats of ATSC

digital TV standard

• Supports picture decoding capability up to

1920x1088 30 Frame/Sec

• Supports all kinds of motion compensation

methods of MPEG-2

• Supports MPEG-2 error code, syntax error

detection, and slice-based error concealment

• Supports DTS synchronization

• Supports VBV delay mode and low delay

mode decoding

• Supports film mode decoding (3:2 Pull

down)

• Supports high level commands for trick

mode

• Supports 8(w)x64(d) internal user data FIFO

• Outputs: macroblock format

4-pel parallel output

54 MHz synchronous I/F

Data window (pdwin, sclk, and mbclk)

Picture information (Picture structure, Field

parity, and DCT type)

• External memory for VBV buffer , DTS

FIFO and 2-frame memory:

64-bit Data Bus

81 MHz Synchronous Interface

64-Mbyte

Four 16x1M SDRAMs

• Host processor interface: I2C bus interface

Two interrupt signals

Supports 23 programmable internal

registers

5

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