MX10EXAQC 查看數據表（PDF） - Macronix International

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MX10EXAQC

XA 16-bit Microcontroller Family 64K Flash/2K RAM, Watchdog, 2UARTs

Macronix International 

MX10EXA

New Enhanced Mode 0

For timers T0 or T1 the 13-bit count mode on the 80C51

(current Mode 0) has been replaced in the XA with a 16-

bit auto-reload mode. Four additional 8-bit data registers

(two per timer: RTHn and RTLn) are created to hold the

auto-reload values. In this mode, the TH overflow will set

the TF flag in the TCON register and cause both the TL

and TH counters to be loaded from the RTL and RTH

registers respectively.

These new SFRs will also be used to hold the TL reload

data in the 8-bit auto-reload mode (Mode 2) instead of

TH.

The overflow rate for Timer 0 or Timer 1 in Mode 0 may

be calculated as follows:

Timer_Rate = Osc/(N*(65536 - Timer_Reload_Value))

where N = the TCLK prescaler value: 4 (default), 16, or

64.

Mode 1

Mode 1 is the 16-bit non-auto reload mode.

Mode 2

Mode 2 configures the Timer register as an 8-bit Counter

(TLn) with automatic reload. Overflow from TLn not only

sets TFn, but also reloads TLn with the contents of RTLn,

which is preset by software. The reload leaves THn un-

changed.

Mode 2 operation is the same for Timer/Counter 0.

The overflow rate for Timer 0 or Timer 1 in Mode 2 may

be calculated as follows:

Timer_Rate = Osc/(N * (256 - Timer_Reload_Value))

where N = the TCLK prescaler value: 4, 16, or 64.

Mode 3

Timer 1 in Mode 3 simply holds its count. The effect is

the same as setting TR1 =0.

Timer 0 in Mode 3 establishes TL0 and TH0 as two sepa-

rate counters. TL0 uses the Timer 0 control bits: CIT;

GATE, TR0, INT0, and TF0. TH0 is locked into a timer

function and takes over the use of TR1 and TF1 from

Timer 1. Thus, TH0 now controls the "Timer 1" interrupt.

Mode 3 is provided for applications requiring an extra 8-

bit timer. When Timer 0 is in Mode 3, Timer 1 can be

turned on and off by switching it out of and into its own

Mode 3, or can still be used by the serial port as a baud

rate generator, or in fact, in any application not requiring

an interrupt.

TCON Address:410 MSB

LSB

Bit Addressable

Reset Value:00H

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

BIT

TCON.7

TCON.6

TCON.5

TCON.4

TCON.3

TCON.2

TCON.2

TCON.0

SYMBOL

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

FUNCTION

Timer 1 overflow flag. Set by hardware on Timer/Counter overflow.

This flag will not be set if T1OE(TSTAT.2) is set.

Cleared by hardware when processor vectors to interrupt routine, or by clearing the bit

in software.

Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off.

Timer 0 overflow flag. Set by hardware on Timer/Counter overflow.

This flag will not be set if T0OE (TSTAT.0) is set.

Cleared by hardware when processor vectors to interrupt routine, or by clearing the bit

in software.

Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off.

Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected.

Cleared when interrupt processed.

Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level

triggered external interrupts.

Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected.

Cleared when interrupt processed.

Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/tow level

triggered external interrupts.

Figure 7. Timer/Counter(TCON) Register

P/N:PM0625 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.0, JUL. 01, 2005

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