ACS760ELF-20B(2013) 查看數據表（PDF） - Allegro MicroSystems

零件编号

产品描述 (功能)

比赛名单

ACS760ELF-20B
(Rev.:2013)

12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC

Allegro MicroSystems 

ACS760ELF-20B

12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC

Features and Benefits

▪ Hall-effect current monitor—no external sense resistor required

▪ Analog output voltage (factory trimmed for gain and

offset) proportional to applied current

▪ External high-side FET gate drive

▪ 240V*A Power Fault Protection with user-programmable delay

▪ User programmable Overcurrent Fault Protection with

programmable delay

▪ 1.5 mΩ internal conductor resistance

▪ Short Circuit Protection isolates failed supply from

output in < 2 μs

▪ Active low Fault indicator output signal

▪ External FET failure detection with active low S1 Short

failure indicator output signal

▪ User controlled soft start / hot-swap function

▪ Logic enable input pin

▪ 10.8 to 13.2 V, single-supply operation

▪ 2 kV ESD protection for all pins

Package: 24 pin QSOP (suffix LF)

Description

The ACS760 combines Allegro™ Hall-effect current sense

technology with a hot-swap controller resulting in a more

efficient integrated controller for 12 V applications. By

eliminating the need for a shunt resistor, the I2R losses in the

power path are reduced.

When the ACS760 is externally enabled, and the voltage rail is

above the internal UVLO threshold, the internal charge pump

drives the gate of the external FET. When a fault is detected, the

gate is disabled while simultaneously alerting the application

that a fault has occurred.

The integrated protection in the ACS760 incorporates three

levels of fault protection, which includes a Power Fault with

user-programmable delay, a user-programmable Overcurrent

Fault threshold with programmable delay, and Short Circuit

protection, which disables the gate in less then 2 μs.

Additionally, in the event the external high-side FET fails

short, the ACS760 detects the S1 Short failure and immediately

disables the gate and alerts the host system. Unlike the three

protection faults, cycling the EN pin does not reset the S1 Short

failure. Power to the device must be cycled.

Approximate Scale

Typical Application

VS_IN

VS_RET

Backplane

IP

RV1 CIN

A

Enable

REN

CEN

VOUT

RSET

CG

COCD

COPD

1

24

IP+

IP–

2

23

IP+

IP–

3

22

IP+

IP–

4

21

IP+

5

ACS760

IP–

20

IP+

IP–

6

19

IP+

IP–

7

18

EN

GATE

8

17

VIOUT

GND

9

16

ISET

FB–

10

15

CG

FB+

11

14

OCDLY

S1SHORT

12

13

OPDLY

FAULT

S1

RG

RFB

C

A RV1 is required only for inductive loads.

B D1 should be a Schottky for inductive loads, to eliminate over-stress of the ACS760.

C FB– is tied to GND at the point of load.

VLOAD

CLOAD

D1

B

3.3 V

RS1

1 kΩ

RFAULT

1 kΩ

760ELF20B-DS, Rev. 8

Share Link: