IDT72103 查看數據表（PDF） - Integrated Device Technology

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IDT72103

CMOS PARALLEL-SERIAL FIFO 2,048 x 9 and 4,096 x 9

Integrated Device Technology 

IDT72103, IDT72104

CMOS PARALLEL-SERIAL FIFO 2,048 x 9, 4,096 x 9

(1)

INDUSTRIAL TEMPERATURE RANGE

t REF (2)

t WEF

(3)

NOTES:

1. Data is valid on this edge.

2. The Empty Flag is asserted by R in the Parallel-Out mode and is specified by tREF. The EF flag is deasserted by the rising edge of W.

3. First rising edge of Write after EF is set.

Figure 6. Empty Flag Timings in Parallel Out Mode

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tRFF (1)

t WFF

NOTE:

1. For the assertion time, tWFF is used when data is written in the Parallel mode. The FF is de-asserted by the rising edge of R.

Figure 7. Full Flag Timings in Parallel-In Mode

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t WF

t RF

Almost

Empty

Figure 8. Almost-Empty Flag Region

Almost

Empty

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t WF

t RF

Almost

Full

Figure 9. Almost-Full Flag Region

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10

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