IDT72103 查看數據表（PDF） - Integrated Device Technology

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IDT72103

CMOS PARALLEL-SERIAL FIFO 2,048 x 9 and 4,096 x 9

Integrated Device Technology 

IDT72103, IDT72104

CMOS PARALLEL-SERIAL FIFO 2,048 x 9 AND 4,096 x 9

INDUSTRIAL TEMPERATURE RANGE

GENERAL SIGNAL DESCRIPTION

INPUTS:

Data Inputs (D0-D8)

The parallel-in mode is selected by connecting the SI/PI pin

to VCC. D0-D8 are the data input lines.

The serial-input mode is selected by grounding the SI/PI

pin. The D0-D8 lines are control output pins used to program

the serial word width.

Reset (RS)

Reset is accomplished whenever the RS input is taken to

a low state. Both internal read and write pointers are set to the

first location during reset. A reset is required after power up

before a write operation can take place. Both Read (R) and

Write (W) inputs must be HIGH during reset.

Expansion In (XI)

The XI pin is grounded to indicate an operation in the the

single-device mode. In the depth expansion or daisy-chain

mode, the XI pin is connected to the XO pin of the previous

device.

Output Enable (OE)

When OE is HIGH, the parallel output buffers are tristated.

When OE is LOW, both parallel and serial outputs are en-

abled.

Serial Input (SI)

Serial data is read into the serial input register via the Sl pin.

In both depth and serial width expansion modes, the serial-

input signals of the different FlFOs in the expansion array are

connected together.

Write (W)

A write cycle is initiated on the falling edge of W provided

the Full Flag (FF) is not asserted. Data set-up and hold times

must be met with respect to the rising edge of W. Data is

stored in the RAM array sequentially and independently of

any on going read operation.

When the FIFO is full, the FF will go LOW inhibiting further

write operations to prevent data overflow. After a valid read

operation is completed, the FF will go HIGH after tRFF allowing

a valid write to begin.

Read (R)

A read cycle is initiated on the falling edge of R, provided

the EF is not set. Data is accessed on a first-in/first out basis

independent of any on going write operations. After R goes

HIGH, the Data Outputs (Q0-Q8) go to a high-impedance

condition until the next read operation. When all the data has

been read from the FIFO, the EF will go LOW, and Q0-Q8 will

go to a high-impedance state inhibiting further read opera-

tions. After the completion of a valid write operation, the EF will

go HIGH after tWEF allowing a valid read to begin.

First Load/Retransmit (FL/RT)

In the depth-expansion mode, the FL/RT pin is grounded to

indicate that it is the first device loaded. In the single-device

mode, the FL/RT pin acts as the retransmit input. The single-

device mode is initiated by grounding the Expansion-ln (XI)

pin.

The IDT72103/72104 can be made to retransmit data

when the RT input is pulsed LOW. A retransmit operation will

set the internal read pointer to the first location and will not

affect the write pointer. During retransmit, R and W must be

set HIGH and the FF will be affected depending on the relative

locations of the read and write pointers. This feature is useful

when less than 2,048/4,096 writes are performed between

resets. The retransmit feature is not available in the depth

expansion mode.

Serial Input Clock (SICP)

Serial data is read into the serial input register on the rising

edge of the SICP signal. In both depth and serial width

expansion modes, the SICP signals of the different FlFOs in

the expansion array are connected together.

Serial Output Clock (SOCP)

New serial data bits are read from the serial output register

on the rising edge of the SOCP signal. In both depth and serial

width expansion modes, the SOCP signals of the different

FlFOs in the expansion array are connected together.

Serial Input Expansion (SIX)

The SlX pin is tied HIGH for single-device serial or parallel

input operation. In a serial input configuration, the SIX pin of

the least significant device is tied HIGH. The SIX pin of all other

devices is connected to the D8 pin of the previous device.

Serial Output Expansion (SOX)

The SOX pin is tied HIGH for single-device serial or parallel

output operation. In a serial output configuration, the SOX pin

of the least significant device is tied HIGH. The SOX pin of all

other devices is connected to the Q8 pin of the previous

device.

Serial/Parallel Input (SI/PI)

The SI/PI pin programs whether the IDT72103/72104

accepts parallel or serial data as input. When this pin is LOW,

the FIFO expects serial data and the D0-D8 pins become

output pins used to program the write signal and the serial

input word width. For instance, connecting D8 to W will

program a serial word width of 9 bits; connecting D7 to W will

program a serial word width of 8 bits and so on.

Serial/Parallel Output (SO/PO)

The SO/PO pin programs whether the IDT72103/72104

outputs parallel or serial data. When this pin is LOW, the FIFO

expects serial data and the Q0-Q8 pins output signals used to

program the read signal and the serial output word width.

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