MAX1206ETL 查看數據表（PDF） - Maxim Integrated

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MAX1206ETL

40Msps, 12-Bit ADC

Maxim Integrated 

40Msps, 12-Bit ADC

Pin Description (continued)

PIN

11

12–15, 36

17, 34

18

19

20

21

22

23

24

25

26

27

28

29

30

31, 32

33

37

38

39

40

—

NAME

CLKTYP

VDD

OVDD

FUNCTION

Clock Type Definition Input. Connect CLKTYP to GND to define the single-ended clock input. Connect

CLKTYP to OVDD or VDD to define the differential clock input.

Analog Power Input. Connect VDD to a 3.0V to 3.6V power supply. Bypass VDD to GND with a parallel

capacitor combination of ≥2.2µF and 0.1µF. Connect all VDD pins to the same potential.

Output Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with a

parallel capacitor combination of ≥2.2µF and 0.1µF.

DOR

Data Out-of-Range Indicator. The DOR digital output indicates when the analog input voltage is out of

range. When DOR is high, the analog input is beyond its full-scale range. When DOR is low, the analog

input is within its full-scale range.

D11 CMOS Digital Output, Bit 11 (MSB)

D10 CMOS Digital Output, Bit 10

D9 CMOS Digital Output, Bit 9

D8 CMOS Digital Output, Bit 8

D7 CMOS Digital Output, Bit 7

D6 CMOS Digital Output, Bit 6

D5 CMOS Digital Output, Bit 5

D4 CMOS Digital Output, Bit 4

D3 CMOS Digital Output, Bit 3

D2 CMOS Digital Output, Bit 2

D1 CMOS Digital Output, Bit 1

D0 CMOS Digital Output, Bit 0 (LSB)

I.C. Internally Connected. Leave I.C. unconnected.

DAV

Data Valid Output. The DAV is a single-ended version of the input clock that is compensated to correct

for any input clock duty-cycle variations. The MAX1211 evaluation kit (MAX1211EVKIT) utilizes DAV to

latch data (D0–D11) into external back-end digital circuitry.

PD

REFOUT

REFIN

G/T

EP

Power-Down Input. Force PD high for power-down mode. Force PD low for normal operation.

Internal Reference Voltage Output. For internal reference operation, connect REFOUT directly to REFIN

or use a resistive-divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a

≥0.1µF capacitor.

Reference Input. VREFIN = 2 x (VREFP - VREFN). Bypass REFIN to GND with a ≥0.1µF capacitor.

Output Format Select Input. Connect G/T to GND for the two’s complement digital output format. Connect

G/T to OVDD or VDD for the Gray code digital output format.

Exposed Paddle. EP is internally connected to GND. Externally connect EP to GND to achieve specified

performance.

16 ______________________________________________________________________________________

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