MAX1206ETL 查看數據表（PDF） - Maxim Integrated

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MAX1206ETL

40Msps, 12-Bit ADC

Maxim Integrated 

40Msps, 12-Bit ADC

Table 1. Reference Modes

VREFIN

35% VREFOUT to 100% VREFOUT

0.7V to 2.3V

<0.5V

REFERENCE MODE

Internal reference mode. REFIN is driven by REFOUT either through a direct short or a resistive

divider. VCOM = VDD / 2, VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 - VREFIN / 4.

Buffered external reference mode. An external 0.7V to 2.3V reference voltage is applied

to REFIN. VCOM = VDD / 2, VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 - VREFIN / 4.

Unbuffered external reference mode. REFP, REFN, and COM are driven by external

reference sources. VREF is the difference between the externally applied VREFP and VREFN.

Reference Output (REFOUT)

An internal bandgap reference is the basis for all the

internal voltages and bias currents used in the

MAX1206. The power-down logic input (PD) enables

and disables the reference circuit. REFOUT has

approximately 17kΩ to GND when the MAX1206 is in

power-down. The reference circuit requires 10ms to

power up and settle when power is applied to the

MAX1206 or when PD transitions from high to low.

The internal bandgap reference and buffer generate

REFOUT to be 2.048V with a +100ppm/°C temperature

coefficient. Connect an external ≥0.1µF bypass capaci-

tor from REFOUT to GND for stability. REFOUT sources

up to 1.4mA and sinks up to 100µA for external circuits

with a load regulation of 35mV/mA. Short-circuit protec-

tion limits IREFOUT to a 2.1mA source current when

shorted to GND and a 240µA sink current when shorted

to VDD.

Analog Inputs and Reference

Configurations

The MAX1206 full-scale analog input range is ±VREF

with a common-mode input range of VDD / 2 ±0.8V.

VREF is the difference between VREFP and VREFN. The

MAX1206 provides three modes of reference operation.

The voltage at REFIN (VREFIN) sets the reference oper-

ation mode (Table 1).

To operate the MAX1206 with the internal reference, con-

nect REFOUT to REFIN either with a direct short or

through a resistive-divider. In this mode, COM, REFP, and

REFN are low-impedance outputs with VCOM = VDD / 2,

VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 -

VREFIN / 4. The REFIN input impedance is very large

(>50MΩ). When driving REFIN through a resistive-divider,

use resistances ≥10kΩ to avoid loading REFOUT.

Buffered external reference mode is virtually identical to

internal reference mode except that the reference

source is derived from an external reference and not

the MAX1206 REFOUT. In buffered external reference

mode, apply a stable 0.7V to 2.3V source at REFIN.

COM, REFP, and REFN are low-impedance outputs

with VCOM = VDD / 2, VREFP = VDD / 2 + VREFIN / 4, and

VREFN = VDD / 2 - VREFIN / 4.

To operate the MAX1206 in unbuffered external refer-

ence mode, connect REFIN to GND. Connecting REFIN

to GND deactivates the on-chip reference buffers for

COM, REFP, and REFN. With their buffers deactivated,

COM, REFP, and REFN inputs must be driven through

separate, external reference sources. Drive VCOM to

VDD / 2 ±5%, and drive REFP and REFN such that

VCOM = (VREFP + VREFN) / 2. The analog input range is

±(VREFP - VREFN).

All three modes of reference operation require the

same bypass capacitor combination. Bypass COM with

a 0.1µF capacitor in parallel with a ≥2.2µF capacitor to

GND. Bypass REFP and REFN each with a 0.1µF

capacitor to GND. Bypass REFP to REFN with a 1µF

capacitor in parallel with a 10µF capacitor. Place the

1µF capacitor as close to the device as possible.

Bypass REFIN and REFOUT to GND with a 0.1µF

capacitor.

For detailed circuit suggestions, see Figures 12 and 13.

Clock Input and Clock Control Lines

(CLKP, CLKN, CLKTYP, DCE)

The MAX1206 accepts both differential and single-

ended clock inputs. For single-ended clock input opera-

tion, connect CLKTYP to GND, CLKN to GND, and drive

CLKP with the external single-ended clock signal. For

differential clock input operation, connect CLKTYP to

OVDD or VDD and drive CLKP and CLKN with the exter-

nal differential clock signal. To reduce clock jitter, the

external single-ended clock must have sharp falling

edges. Consider the clock input as an analog input and

route it away from any other analog inputs and digital

signal lines.

CLKP and CLKN are high impedance when the

MAX1206 is powered down (Figure 4).

Low clock jitter is required for the specified SNR perfor-

mance of the MAX1206. Analog input sampling occurs

on the falling edge of the clock signal, requiring this

18 ______________________________________________________________________________________

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