MX10FMAXDPC 查看數據表（PDF） - Macronix International
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MX10FMAXDPC Datasheet PDF : 24 Pages
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MX10FMAXDPC
MX10FMAXDQC
PROCESS INFORMATION
This device is manufactured on a MXIC CMOS process.
PIN DESCRIPTIONS
VCC : Supply voltage.
VSS : Circuit ground.
Port 0 : Port 0 is an 8-bit, open drain, bidirectional I/O
port. As an output port each pin can sink several LS
TTL inputs. Port 0 pins that have 1's written to them
float, and in that state can be used as high-impedance
inputs.
Port 0 is also the multiplexed low-order address and data
bus during accesses to external Program and Data
Memory. In this application it uses strong internal pullups
when emitting 1's, and can source and sink serveral LS
TTL inputs.
Port 1 : Port 1 is an 8-bit bidirectional I/O port with inter-
nal pullups. The port 1 output buffers can drive LS TTL
inputs. Port 1 pins that have 1's written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 1 pins that are exter-
nally pulled low will source current (IIL, on the data sheet)
because of the internal pullups.
In additional, Port 1 serves the functions of the following
special features of the MX10C805X :
Port Pin
P1.0
P1.1
Alternate Function
T2 (External Count Input to Timer/
Counter 2), Clock-Out
T2EX (Timer/Counter 2 Capture/Reload
Trigger and Direction Control)
Port 2 : Port 2 is an 8-bit bidirectional I/O port with inter-
nal pullups. The port 2 output buffers can drive LS TTL
inputs. Port 2 pins that have 1's written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 2 pins that are exter-
nally pulled low will source current (IIL, on the data sheet)
because of the internal pullups.
Port 2 emits the high-order address byte during fetches
from external Program Memory and during accesses to
external Data Memory that use 16-bit addresses (MOVX
@DPTR). In this application it uses strong internal
pullups when emitting 1's. During accesses to external
Data Memory that use 8-bit addresses (MOVX @Ri),
Port 2 emits the contents of the P2 Special Function
Register.
Port 3 : Port 3 is an 8-bit bidirectional I/O port with inter-
nal pullups. The port 3 output buffers can drive LS TTL
inputs. Port 3 pins that have 1's written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 3 pins that are exter-
nally pulled low will source current (IIL, on the data sheet)
because of the internal pullups.
Port 3 also serves the function of various special fea-
tures of the 8051 Family, as listed below :
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Function
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write sttobe)
RD (external data memory read strobe)
RST : Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device.
The port pins will be driven to their reset condition when
a minimum VIHI voltage is applied whether the oscilla-
tor is running or not. An internal pulldown resistor per-
mits a power-on reset with only a capacitor connected
to VCC.
ALE : Address Latch Enable output pulse for latching
the low byte of the address during accesses to external
memory.
In normal operation ALE is emitted at a constant rate of
1/6 the oscillator frequency, and may be used for exter-
nal timing or clocking purposes. Note, however, that
one ALE pulse is skipped during each access to exter-
nal Data Memory.
P/N:PM1053 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.0, DEC. 10, 2003
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