MSM80C86A-10GS 查看數據表（PDF） - Oki Electric Industry

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MSM80C86A-10GS

16-Bit CMOS MICROPROCESSOR

Oki Electric Industry 

¡ Semiconductor

MSM80C86A-10RS/GS/JS

Minimum and Maximum Modes

The MSM80C86A-10 has two system modes: minimum and maximum. When using maximum

mode, it is easy to organize a multi-CPU system with a MSM82C88-2 Bus Controller which

generates the bus control signal.

When using minimum mode, it is easy to organize a simple system by generating bus control

signal by itself.

MN/MX is the mode select pin. Definition of 24-31 pin changes depend on the MN/MX pin.

Bus Operation

The MSM80C86A-10 has a time multiplexed address and data bus. If a non-multiplexed bus is

desired for a system, it is only to add the address latch.

A CPU bus cycle consists of at least four clock cycles: T1, T2, T3 and T4. (Fig. 4)

The address output occurs during T1 and data transfer occurs during T3 and T4. T2 is used for

changing the direction of the bus at the read operation. When the device which is accessed by

the CPU is not ready for The data transfer and the CPU “NOT READY”, TW cycles are inserted

between T3 and T4.

When a bus cycle is not needed, T1 cycles are inserted between the bus cycles for internal

execution. During the T1 cycle, the ALE signal is output from the CPU or the MSM82C88-2

depending on MN/MX. At the trailing edge of ALE, a valid address may be latched.

Status bits S0, S1 and S2 are used in the maximum mode by the bus controller to recognize the

type of bus operation according to the following table.

Status bits S3 through S7 are multiplexed with A16 - A19, and BHE: therefore, they are valid

during T2 through T4.

S3 and S4 indicate which segment register was selected on the bus cycle, according to the

following table.

S2

S1

0 (LOW) 0

0

0

0

1

0

1

1 (HIGH) 0

1

0

1

1

1

1

S0

Characteristics

0 Interrupt acknowledge

1 Read I/O

0 Write I/O

1 Halt

0 Instruciton Fetch

1 Read Data from Memory

0 Write Data to Memory

1 Passive (no bus cycle)

S4

S3

0 (LOW) 0

0

1

1 (HIGH) 0

1

1

Characteristics

Alternate Data (Extra segment)

Stack

Code or None

Data

S5 indicates interrupt enable Flag.

I/O Addressing

The MSM80C86A-10 has 64 Kbytes of I/O or as 32 Kwords I/O. When the CPU accesses an I/

O device, addresses AD0 - AD15 are in the same format as a memory address, and A16 - A19 are

low.

The I/O ports addresses are same as memory, so it is necessary to be careful when using 8-bit

peripherals.

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