MSM80C86A-10GS 查看數據表（PDF） - Oki Electric Industry

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MSM80C86A-10GS

16-Bit CMOS MICROPROCESSOR

Oki Electric Industry 

¡ Semiconductor

MSM80C86A-10RS/GS/JS

EXTERNAL INTERFACE

Reset

CPU Initialization is executed by the RESET pin. The MSM80C86A-10’s RESET High signal is

required for greater than 4 clock cycles.

The Rising edge of RESET terminates present operation immediately. The Falling edge of

RESET triggers an internal reset sequence for approximately 10 clock cycles. After the internal

reset sequence is finished normal operation occurs from absolute location FFFF0H.

Interrupt Operations

Interrupt operation is classified as software or hardware, and hardware interrupt is classified

as non-maskable or maskable.

An interrupt causes a new program location defined on the interrupt pointer table, according

to the interrupt type. Absolute locations 00000H through 003FFH are reserved for the interrupt

pointer table. The interrupt pointer table consists of 256-elements. Each element is 4 bytes in

size and corresponds to an 8-bit type number which is sent from an interrupt request device

during the interrupt acknowledge cycle.

Non-maskable Interrupt (NMI)

The MSM80C86A-10 has a Non-maskable interrupt (NMI) which is of higher priority than the

markable interrupt request (INTR).

The NMI request pulse width needs a minimum of 2 clock cycles. The NMI will be serviced at

the end of the current instruction or between string manipulations.

Maskable Interrupt (INTR)

The MSM80C86A-10 provides another interrupt request (INTR) which can be masked by

software. INTR is level triggered, so it must be held until the interrupt request is acknowledged.

INTR will be serviced at the end of the current instruction or between string manipulations.

Interrupt Acknowledge Sequence

ALE

LOCK

INTA

AD0 - AD15

T1

T2

T3 T4 TI T1

T2

T3

T4

Float

Type Vector

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