SC1205 查看數據表（PDF） - Samtec

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SC1205

High Speed Synchronous Power MOSFET Driver

Samtec 

POWER MANAGEMENT

Block Diagram

SC1205

Applications Information

SC1205 is a high speed, smart dual MOSFET driver. It is

designed to drive Low Rds_On power MOSFET’s with

ultra-low rise/fall times and propagation delays. As the

switching frequencies of PWM controllers is increased to

reduce power supply volume and cost, fast rise and fall

times are necessary to minimize switching losses (TOP

MOSFET) and reduce Dead-time (BOTTOM MOSFET).

While Low Rds_On MOSFET’s present a power saving in

I2R losses, the MOSFET’s die area is larger and thus the

effective input gate capacitance of the MOSFET is in-

creased. Often a 50% decrease in Rds_On more than

doubles the effective input gate charge, which must be

supplied by the driver. The Rds_On power savings can

be offset by the switching and dead-time losses with a

sub_optimum driver. While discrete solutions can achieve

reasonable drive capability, implementing shoot-through

and other housekeeping functions necessary for safe

operation can become cumbersome and costly. The

SC120X family of parts presents a total solution for the

high-speed high power density applications. Wide input

supply range of 4.5V-25V allows use in battery powered

applications, new high voltage, distributed power serv-

ers as well as Class-D amplifiers.

THEORY OF OPERATION

The control input (CO) to the SC1205 is typically supplied

by a PWM controller that regulates the power supply out-

put. (See Application Evaluation Schematic, Figure 4).

The timing diagram demonstrates the sequence of events

by which the top and bottom drive signals are applied.

The shoot-through protection is implemented by holding

the bottom FET off until the voltage at the phase node

(intersection of top FET source, the output inductor and

the bottom FET drain) has dropped below 1V. This as-

sures that the top FET has turned off and that a direct

current path does not exist between the input supply

and ground. The top FET Gate Drive is turned on after

the bottom gate drive has gone low and an internal delay

time of 20ns has expired.

LAYOUT GUIDELINES

As with any high speed , high current circuit, proper lay-

out is critical in achieving optimum performance of the

SC1205. The Evaluation board schematic (Refer to fig-

ure 3) shows a two-phase synchronous design with all

surface mountable components.

While components connecting to EN are relatively non-

critical, tight placement and short, wide traces must be

used in layout of The gate drives, DRN, and especially

PGND pin. The top gate driver supply voltage is provided

by bootstrapping the +5V supply and adding it to the

phase node (DRN) voltage . Since the bootstrap capaci-

tor supplies the charge to the top gate, it must be less

than .5” away from the SC1205. Ceramic X7R capaci-

tors are a good choice for supply bypassing near the chip.

The Vcc pin capacitor must also be less than .5” away

from the SC1205. The ground node of this capacitor,

 2004 Semtech Corp.

6

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