SC18IS600 查看數據表（PDF） - NXP Semiconductors.
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SC18IS600 Datasheet PDF : 30 Pages
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NXP Semiconductors
SC18IS600
SPI to I2C-bus interface
Table 3. Pin description …continued
Symbol
Pin
Type Description
TSSOP16 HVQFN24
WAKEUP/IO4 15
18
I/O Wake up the SC18IS600 from the Power-down mode. Pulled LOW by
the host to wake-up from low power state. This pin can also be used as
a quasi-bidirectional I/O when not in a power-down state.
IO5
16
20
I/O quasi-bidirectional I/O pin
n.c.
-
7, 9, 10, 12, -
19, 21, 22,
24
not connected
[1] HVQFN24 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
6. Functional description
The SC18IS600 acts as a bridge between a SPI interface and an I2C-bus. It allows a SPI
master device to communicate with I2C-bus slave devices. The SPI interface supports
Mode 3 of the SPI specification and can operate up to 1.2 Mbit/s.
6.1 Internal registers
The SC18IS600 provides internal registers for monitoring and control. These registers are
shown in Table 4. Register functions are more fully described in the following paragraphs.
Table 4. Internal registers summary
Register Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
R/W
address
0x00
IOConfig IO3.1 IO3.0 IO2.1 IO2.0 IO1.1
IO1.0
IO0.1
IO0.0
R/W
0x01
IOState 0
0
GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 R/W
0x02
I2CClock CR7 CR6 CR5 CR4 CR3
CR2
CR1
CR0
R/W
0x03
I2CTO TO6 TO5 TO4 TO3 TO2
TO1
TO0
TE
R/W
0x04
I2CStat 1
1
1
1
I2CSTAT3 I2CSTAT2 I2CSTAT1 I2CSTAT0 R
0x05
I2CAdr ADR7 ADR6 ADR5 ADR4 ADR3
ADR2
ADR1
X
R/W
Default
value
0x00
0x3F
0x19
0xFE
0xF0
0x00
6.2 Register descriptions
6.2.1 Programmable IO port configuration register (IOConfig)
Pins GPIO0 to GPIO3 may be configured by software to one of four types. These are:
quasi-bidirectional, push-pull, open-drain, and input-only. Two configuration bits per pin,
located in the IOConfig register, select the IO type for each pin. Each pin has
Schmitt-triggered input that also has a glitch suppression circuit. IO4 and IO5 are
quasi-bidirectional pins and are not user-configurable.
Table 5 shows the configurations for the programmable I/O pins. IOx.1 and IOx.0
correspond to GPIOx.
SC18IS600
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7.1 — 20 November 2017
© NXP Semiconductors N.V. 2017. All rights reserved.
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