V54C316162V-5 查看數據表（PDF） - Mosel Vitelic, Corp

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V54C316162V-5

200/183/166/143 MHz 3.3 VOLT/ 4K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16

Mosel Vitelic, Corp 

MOSEL VITELIC

1. Bank Activate Command Cycle

(CAS latency = 3)

T0

T1

T

CLK

ADDRESS

Bank A

Row Addr.

COMMAND

: “H” or “L”

Bank A

Activate

tRCD

NOP

NOP

V54C316162V

T

T

T

T

..........

Bank A

..........

Bank B

Col. Addr.

Row Addr.

tRRD

Write A

with Auto

Precharge

..........

Bank B

Activate

NOP

tRC

Bank A

Row Addr.

Bank A

Activate

2. Burst Read Operation

(Burst Length = 4, CAS latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

COMMAND READ A

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CAS latency = 2

tCK2, I/O’s

CAS latency = 3

tCK3, I/O’s

DOUT A0

DOUT A1

DOUT A2

DOUT A3

DOUT A0

DOUT A1

DOUT A2

DOUT A3

NOP

V54C316162V Rev. 2.9 September 2001

13

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