V54C316162V 查看數據表（PDF） - Mosel Vitelic, Corp

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V54C316162V

200/183/166/143 MHz 3.3 VOLT/ 4K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16

Mosel Vitelic, Corp 

MOSEL VITELIC

V54C316162V

3. Read Interrupted by a Read

(Burst Length = 4, CAS latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

COMMAND READ A

READ B

NOP

NOP

NOP

NOP

NOP

NOP

NOP

CAS latency = 2

tCK2, I/O’s

DOUT A0

DOUT B0

DOUT B1

DOUT B2

DOUT B3

CAS latency = 3

tCK3, I/O’s

4.1 Read to Write Interval

(Burst Length = 4, CAS latency = 3)

T0

T1

T2

CLK

DOUT A0

DOUT B0

DOUT B1

DOUT B2

DOUT B3

T3

T4

T5

T6

T7

T8

DQM

COMMAND NOP

Minimum delay between the Read and Write Commands = 4+1 = 5 cycles

tDQZ

tDQW

READ A

NOP

NOP

NOP

NOP

WRITE B

NOP

NOP

I/O’s

: “H” or “L”

DOUT A0

Must be Hi-Z before

the Write Command

DIN B0

DIN B1

DIN B2

V54C316162V Rev.2.9 September 2001

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