V54C316162V 查看數據表（PDF） - Mosel Vitelic, Corp

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V54C316162V

200/183/166/143 MHz 3.3 VOLT/ 4K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16

Mosel Vitelic, Corp 

MOSEL VITELIC

6.2 Write Interrupted by a Read

(Burst Length = 4, CAS latency = 2, 3)

V54C316162V

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

COMMAND NOP

WRITE A

READ B

NOP

NOP

NOP

NOP

NOP

NOP

CAS latency = 2

tCK2, I/O’s

CAS latency = 3

tCK3, I/O’s

DIN A0

don’t care

DOUT B0 DOUT B1 DOUT B2 DOUT B3

DIN A0

don’t care don’t care

DOUT B0 DOUT B1 DOUT B2 DOUT B3

Input data must be removed from the I/O’s at least one clock

cycle before the Read dataAPpears on the outputs to avoid

data contention.

7. Burst Write with Auto-Precharge

Burst Length = 2, CAS latency = 2, 3)

CLK

T0

T1

T2

T3

T4

T5

T6

T7

T8

COMMAND

BANK A

ACTIVE

NOP

CAS latency = 2

I/O’s

CAS latency = 3

I/O’s

NOP

WRITE A

Auto-Precharge

DIN A0

DIN A0

NOP

NOP

tWR

DIN A1

*

tWR

DIN A1

*

NOP

tRP

NOP

tRP

* Begin Autoprecharge

Bank can be reactivated after trp

NOP

V54C316162V Rev. 2.9 September 2001

17

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