GLT5160L16I-10FJ 查看數據表（PDF） - G-Link Technology

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GLT5160L16I-10FJ

16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM

G-Link Technology  

Read

After tRCD from the bank activation, a READ command can be

issued. 1st output data is available after the CAS Latency from the

READ, followed by (BL-1) consecutive data when the Burst Length

is BL. The start address is specified by A[7:0], and the address

sequence of burst data is defined by the Burst Type. A READ com-

mand may be applied to any active bank, so the row precharge time

(tRP) can be hidden behind continuous output data (in case of BL =

4) by interleaving the dual banks. When A[10] is high at a READ

command, the auto-precharge (READA) is performed. Any com-

mand (READ, WRITE, PRE, ACT) to the same bank is inhibited till

the internal precharge is complete. The internal precharge start tim-

ing depends on CAS Latency. The next ACT command can be

issued after tRP from the internal precharge timing.

CLK

Command

A[9:0]

A[10]

BA

DQ

ACT

Xa

tRCD

REA

Ya

ACT

Xb

REA

PRE

Yb

Xa

0

Xb

0

0

0

0

1

1

0

Burst Length

Qa0

Qa1

Qa2

Qa3

Qb0

Qb1

Qb2

CAS Latency

Figure 4. Dual Bank Interleaving READ (BL=4, CL=3)

CLK

Command

A[9:0]

A[10]

BA

DQ

ACT

Xa

tRCD

READ A

Y

ACT

tRP

Xa

Xa

1

Xa

0

0

0

Qa0

Qa1

Qa2

Qa3

Internal Precharge begins

Figure 5. READ with Auto-Precharge (BL=4, CL=3)

CLK

Command

CL=3 DQ

CL=2 DQ

ACT

READ A

Qa0

Qa1

Qa2

Qa3

Qa0

Qa1

Qa2

Qa3

Internal Precharge Start Timing

Figure 6. READ Auto-Precharge Timing (BL=4)

G-LINK Technology

11

DEC. 2003 (Rev.2.4)

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