GLT5160L16I-10FJ 查看數據表（PDF） - G-Link Technology
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GLT5160L16I-10FJ Datasheet PDF : 45 Pages
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Write
After tRCD from the bank activation, a WRITE command can be
issued. 1st input data is set at the same cycle as the WRITE. Follow-
ing (BL-1) data are written into the RAM, when the Burst Length is
BL. The start address is specified by A[7:0], and the address
sequence of burst data is defined by the Burst Type. A WRITE com-
mand may be applied to any active bank, so the row precharge time
(tRP) can be hidden behind continuous input data (in case of BL = 4)
by interleaving the dual banks. From the last input data to the PRE
command, the write recovery time (tRDL) is required. When A[10]
is high at a WRITE command, the auto-precharge (WRITEA) is
performed. Any command (READ, WRITE, PRE, ACT) to the
same bank is inhibited till the internal precharge is complete. The
internal precharge begins at tWR after the last input data cycle. The
next ACT command can be issued after tRP from the internal pre-
charge timing.
CLK
Command
A[9:0]
A[10]
BA
DQ
ACT
Xa
Xa
0
tRCD
WRITE ACT
Y
Xb
0
Xb
tRCD
WRITE PRE
Y
tRDL (1
0
0
0
1
1
0
Burst Length
Da0
Da1
Da2
Da3
Db0
Db1
Db2
Db3
Figure 7. Dual Bank Interleaving WRITE (BL=4)
CLK
Command
A[9:0]
A[10]
BA
DQ
ACT
Xa
Xa
0
tRCD
WRITE
Y
1
0
Da0
Da1
tRDL
Da2
Da3
ACT
tRP
Xa
Xa
0
Internal Precharge Begins
Figure 8. WRITE with Auto-Precharge (BL=4)
12
G-LINK Technology
DEC. 2003 (Rev. 2.4)
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