GLT5160L16I-10FJ 查看數據表（PDF） - G-Link Technology

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GLT5160L16I-10FJ

16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM

G-Link Technology  

Power On Sequence

Before starting normal operation, the following power on sequence

is necessary to prevent damage or malfunction.

1. Apply power and start clock. Attempt to maintain CKE high,

DQMU / DQML high and NOP condition at the inputs.

2. Maintain stable power, stable clock, and NOP input condi-

tions for a minimum of 200 µs.

3. Issue precharge commands for all banks. (PRE or PREA)

4. After all banks become idle state (after tRP), issue 2 or more

auto-refresh commands.

5. Issue a mode register set command to initialize the mode

register.

After this sequence, the SDRAM is idle state and ready for normal

operation.

SELF

REFRESH

MODE

REGISTER

SET

MRS

REF

REFS

IDLE

AUTO

REF

REFRESH

CLK

SUSPEND

CKE

CKE

ACT

POWER

DOWN

CKE

CKE

WRITE

SUSPEND

CKE

CKE

WRITE

ROW

TBST

WRIT

TBST

REA

WRITE

READE

READ

WRITE

READ

CKE

CKE

READ

SUSPEND

WRITE

WRITE A

SUSPEND

CKE

CKE

WRITE A

WRITE

READE

PRE

PRE

PRE

POWER

APPLIED

POWER ON

PRE

PRECHARGE

READE

READ A

CKE

CKE

READ A

SUSPEND

Automatic Sequence

Command Sequence

Figure 2. Simplified State Diagram

8

G-LINK Technology

DEC. 2003 (Rev. 2.4)

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