4501 查看數據表（PDF） - MITSUBISHI ELECTRIC

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4501

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MITSUBISHI ELECTRIC  

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

PERFORMANCE OVERVIEW

Parameter

Function

Number of basic instructions

111

Minimum instruction execution time

0.68 µs (at 4.4 MHz oscillation frequency, in high-speed mode)

Memory sizes ROM M34501M2 2048 words ✕ 10 bits

M34501M4/E4 4096 words ✕ 10 bits

RAM M34501M2 128 words ✕ 4 bits

M34501M4/E4 256 words ✕ 4 bits

Input/Output D0–D3 I/O

ports

Four independent I/O ports.

Input is examined by skip decision.

Ports D2 and D3 are equipped with a pull-up function and a key-on wakeup function. Both func-

tions can be switched by software.

Ports D2 and D3 are also used as ports C and K, respectively.

P00–P03 I/O

4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both

functions can be switched by software.

P10–P13 I/O

4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both

functions can be switched by software.

Ports P12 and P13 are also used as CNTR and INT, respectively.

P20, P21 I/O

2-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both

functions can be switched by software.

Ports P20 and P21 are also used as AIN0 and AIN1, respectively.

C

I/O

1-bit I/O; Port C is also used as port D2.

K

I/O

1-bit I/O; Port K is also used as port D3.

CNTR Timer I/O

1-bit I/O; CNTR pin is also used as port P12.

INT

Interrupt input 1-bit input; INT pin is also used as port P13.

AIN0, AIN1 Analog input Two independent I/O ports. AIN0–AIN1 is also used as ports P20, P21, respectively.

Timers

Timer 1

8-bit programmable timer with a reload register.

Timer 2

8-bit programmable timer with a reload register and has a event counter.

A-D converter

10-bit wide, This is equipped with an 8-bit comparator function.

Analog input

2 channel (AIN0 pin, AIN1 pin)

Interrupt

Sources

4 (one for external, two for timer, one for A-D)

Nesting

1 level

Subroutine nesting

8 levels

Device structure

CMOS silicon gate

Package

20-pin plastic molded SOP (20P2N-A)

Operating temperature range

–20 °C to 85 °C

Supply voltage

VRST to 5.5 V (VRST: detected voltage of voltage drop detection circuit. Refer to the voltage

drop detection circuit characteristics.)

Power

Active mode

dissipation

1.7 mA (at VDD = 5.0 V, 4.0 MHz oscillation frequency, in high-speed mode, output transistors

in the cut-off state)

(typical value) RAM back-up mode

0.1 µA (at room temperature, VDD = 5 V, output transistors in the cut-off state)

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