MAX1160 查看數據表（PDF） - Maxim Integrated
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MAX1160 Datasheet PDF : 8 Pages
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10-Bit, 20Msps, TTL-Output ADC
Table 2. Output Data Information
ANALOG
INPUT
> +2V + 1/2LSB
+2V - 1LSB
0V
-2V + 1LSB
< 2V
OVERRANGE
D10
1
0
0
0
0
OUTPUT CODE
D9–D0
11 1111 1111
11 1111 111Ø
ØØ ØØØØ ØØØØ
00 0000 000Ø
00 0000 0000
(Ø indicates the flickering bit between logic 0 and 1.)
50% to optimize performance, but performance will not
be degraded if kept within the 40% to 60% range. The
analog input signal is latched on the rising edge of CLK.
The clock input must be driven from fast TTL logic
(VIH ≤ 4.5V, tRISE < 6ns). In the event the clock is dri-
ven from a high current source, use a 100Ω resistor
(R5) in series to limit current to approximately 45mA.
Digital Outputs
The format of the output data (D0–D9) is straight binary
(Table 2). The outputs are latched on the rising edge of
CLK with a typical propagation delay of 14ns. There is
a one-clock-cycle latency between CLK and the valid
output data (Figure 1a).
The digital outputs’ rise and fall times are not symmetri-
cal. Typical propagation delay is 14ns for the rise time
and 6ns for the fall time (Figure 4). The nonsymmetri-
cal rise and fall times create approximately 8ns of in-
valid data.
Overrange Output
The overrange output (D10) is an indication that the
analog input signal has exceeded the positive full-scale
input voltage by 1LSB. When this condition occurs,
D10 will switch to logic 1. All other data outputs
(D0–D9) will remain at logic 1 as long as D10 remains
at logic 1. This feature makes it possible to include the
MAX1160 in higher-resolution systems.
Evaluation Board
The MAX1160 EV kit is available to help designers
demonstrate the MAX1160’s full performance. This
board includes a reference circuit, a clock-driver cir-
cuit, output data latches, and an on-board reconstruc-
tion of the digital data. A separate data sheet
describing the operation of this board is also available.
Contact the factory for price and availability.
VCC
VIN
VFT
VEE
Figure 3. Analog Equivalent Input Circuit
N
N+1
CLK IN 2.4V
6ns
typ
3.5V
DATA 2.4V
OUT
(ACTUAL) 0.8V
0.5V
(N - 2)
INVALID
DATA
tpd1
14ns typ
DATA OUT (N - 2)
(EQUIVALENT)
INVALID
DATA
(N - 1)
(N - 1)
tRISE
6ns
INVALID
DATA
N
INVALID N
DATA
Figure 4. Digital Output Characteristics
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 ___________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1997 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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