MT9M011 查看數據表（PDF） - Micron Technology

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MT9M011

1/3-Inch Megapixel CMOS Active-Pixel Digital Image Sensor

Micron Technology 

Preliminary‡

MT9M011 - 1/3-Inch Megapixel Image Sensor

Registers

Table 7: Register Description (Continued)

Bit

Bit Description

0x08 (8) Vertical Blanking A

14:0 Vertical

Blanking A

Number of blank rows in a frame when context A is

chosen (Reg0xC8, bit 1 = 1). This number must be equal

to or larger than the number of dark rows read out in a

frame specified by Reg0x22.

0x09 (9) Shutter Width

15:0 Shutter Width

Integration time in number of rows. In addition to this

register the shutter delay register (Reg0x0C) and the

overhead time will influence the integration time for a

given row time.

0x0A (10) Row Speed

3:0 Pixel Clock

Period

Pixel clock period in master clocks when two ADCs are

used (Reg0x20/0x21, bit 10 = 0). The ADC clock will

always be half the programmed frequency. When only

one ADC is used the pixel clock frequency will be

halved as well, so in this case will be equal to the ADC

clock frequency. The value “0” is not allowed, “1” will

be used instead.

7:4 Delay Pixel

Clock

Delay PIXCLK in half master clock cycles. When set the

pixel clock can be delayed in increments of half master

clock cycles compared to the synchronization of

FRAME_VALID, LINE_VALID and DATA_OUT.

8 Invert Pixel

Clock

Invert pixel clock. When set, LINE_VALID, FRAME

_VALID, and DATA_OUT will be set up to the falling

edge of PIXCLK. When clear, they are set up to the

rising edge if there are no delay of the pixel clock.

15:14 Reserved

–

0x0B (11) Extra Delay

13:0 Extra Delay

Extra blanking inserted between frames specified in

pixel clocks. Can be used to get a more exact frame

rate. It might affect the integration times of parts of

the image when the integration time is less than one

frame.

0x0C (12) Shutter Delay

10:0 Shutter Delay

The amount of time from the end of the sampling

sequence to the beginning of the pixel reset sequence.

This variable will automatically be halved when one

ADC is used so the time in us will remain the same. This

register has an upper value defined by the fact that the

reset needs to finish before the readout of that row to

prevent changes in the row time.

Default

(Hex)

19

432

1

1

0

0

0

0

Sync’d

to

Frame

Start

Y

Y

Y

N

N

–

Y

Y

Bad

Frame

N

N

YM

–

N

Read/

write

W

W

W

W

W

–

W

W

PDF: 09005aef81051c04/Source: 09005aef8102abe8

MT9M011_2.fm - Rev. D 1/05 EN

20

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2004 Micron Technology, Inc. All rights reserved.

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