TC78B002FTG 查看數據表（PDF） - Toshiba

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TC78B002FTG

TOSHIBA CMOS Integrated Circuit Silicon Monolithic

Toshiba 

Timing chart (Lock protection)

TC78B002FTG

2. VSP/ VMI Input Pin

Output starts when VSP pin at the voltage of more than VAD(L). And it turns off at the voltage of VAD(L) or less.

Minimum voltage of VSP pin is clipped by the voltage of VMI pin.

In case the minimum duty setting by VMI pin is not used, connect the VMI pin to the GND pin.

Analog voltage which is input to VSP pin and VMI pin is converted by AD convertor of 7 bit, and the output

PWM duty is controlled.

0

≤ VSP, VMI ≤ VAD (L) → Duty = 0%

VAD (L) < VSP, VMI ≤ VAD (H) → Below figure (17/127 to 116/127)

VAD (H) < VSP, VMI ≤ VREG

→ Duty = 100% (117/127 to 127/127)

(PWM duty indicates the peak value of output because this circuit has a soft switching function.)

3. Hall Input Signal

Characteristics of hall signal shown below are inputted to the hall input pin.

VH: 40mV or more

VHHYS+=10mV, VHHYS-=-10mV

*Though hall amplifier operates when VH is 40mV or

more, please widen the oscillation as possible to

stabilize the time width.

(200mV or more is recommended.)

13

2013-03-19

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