74HC595PW-Q100(2017) 查看數據表（PDF） - NXP Semiconductors.
零件编号
产品描述 (功能)
比赛名单
74HC595PW-Q100
(Rev.:2017)
(Rev.:2017)
NXP Semiconductors.
74HC595PW-Q100 Datasheet PDF : 23 Pages
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Nexperia
74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Symbol Parameter Conditions
tdis
disable time OE to Qn; see Figure 13
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
tW
pulse width SHCP HIGH or LOW;
see Figure 9
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
STCP HIGH or LOW;
see Figure 10
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
MR LOW; see Figure 12
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
tsu
set-up time DS to SHCP; see Figure 11
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
SHCP to STCP;
see Figure 11
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
th
hold time DS to SHCP; see Figure 11
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
trec
recovery MR to SHCP; see Figure 12
time
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
25 °C
Min Typ [1] Max
[4]
-40 °C to
+85 °C
Min Max
-40 °C to Unit
+125 °C
Min Max
-
41 150
-
190
-
225 ns
-
15
30
-
38
-
45 ns
-
12
27
-
33
-
38 ns
75
17
15
6
13
5
-
95
-
19
-
16
-
110
- ns
-
22
- ns
-
19
- ns
75
11
15
4
13
3
-
95
-
19
-
16
-
110
- ns
-
22
- ns
-
19
- ns
75
17
15
6
13
5
-
95
-
19
-
16
-
110
- ns
-
22
- ns
-
19
- ns
50
11
10
4
9
3
-
65
-
13
-
11
-
75
- ns
-
15
- ns
-
13
- ns
75
22
15
8
13
7
-
95
-
19
-
16
-
110
- ns
-
22
- ns
-
19
- ns
3
-6
-
3
-
3
- ns
3
-2
-
3
-
3
- ns
3
-2
-
3
-
3
- ns
50 -19
-
65
-
75
- ns
10
-7
-
13
-
15
- ns
9
-6
-
11
-
13
- ns
74HC_HCT595_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 28 February 2017
© Nexperia B.V. 2017. All rights reserved.
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