74HC595PW-Q100(2017) 查看數據表（PDF） - NXP Semiconductors.
零件编号
产品描述 (功能)
比赛名单
74HC595PW-Q100
(Rev.:2017)
(Rev.:2017)
NXP Semiconductors.
74HC595PW-Q100 Datasheet PDF : 23 Pages
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Nexperia
74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Symbol Parameter Conditions
II
IOZ
ICC
ΔICC
CI
input leakage VI = VCC or GND; VCC = 5.5 V
current
OFF-state
VI = VIH or VIL; VCC = 5.5 V;
output current VO = VCC or GND
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
additional
supply current
per input pin;
other inputs at VCC or GND;
IO = 0 A; VI = VCC - 2.1 V;
VCC = 4.5 V to 5.5 V
pins MR, SHCP, STCP, OE
pin DS
input
capacitance
-40 °C to +85 °C
Min Typ Max
-
-
±1.0
-
-
±5.0
-
-
80
-
150
675
-
25
113
-
3.5
-
-40 °C to +125 °C Unit
Min
Max
-
±1.0 μA
-
±10 μA
-
160 μA
-
735 μA
-
123 μA
-
-
pF
11 Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14.
Symbol Parameter Conditions
25 °C
74HC595-Q100
tpd
propagation SHCP to Q7S; see Figure 9
delay
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
STCP to Qn; see Figure 10
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
tPHL
HIGH
MR to Q7S; see Figure 12
to LOW
propagation
VCC = 2 V
delay
VCC = 4.5 V
VCC = 6 V
ten
enable time OE to Qn; see Figure 13
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
Min Typ [1] Max
[2]
-
-
-
[2]
-
-
-
52 160
19
32
15
27
55 175
20
35
16
30
-
-
-
[3]
-
-
-
47 175
17
35
14
30
47 150
17
30
14
26
-40 °C to
+85 °C
Min Max
-
200
-
40
-
34
-
220
-
44
-
37
-
220
-
44
-
37
-
190
-
38
-
33
-40 °C to Unit
+125 °C
Min Max
-
240 ns
-
48 ns
-
41 ns
-
265 ns
-
53 ns
-
45 ns
-
265 ns
-
53 ns
-
45 ns
-
225 ns
-
45 ns
-
38 ns
74HC_HCT595_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 28 February 2017
© Nexperia B.V. 2017. All rights reserved.
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