AD1881A 查看數據表（PDF） - Analog Devices
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AD1881A Datasheet PDF : 26 Pages
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AD1881A
TIMING PARAMETERS1 (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter
Symbol
Min
RESET Active Low Pulsewidth
RESET Inactive to BIT_CLK Startup Delay
SYNC Active High Pulsewidth
SYNC Low Pulsewidth
SYNC Inactive to BIT_CLK Startup Delay
BIT_CLK Frequency
BIT_CLK Period
BIT_CLK Output Jitter2
BIT_CLK High Pulsewidth
BIT_CLK Low Pulsewidth
SYNC Frequency
SYNC Period
Setup to Falling Edge of BIT_CLK
Hold from Falling Edge of BIT_CLK
BIT_CLK Rise Time
BIT_CLK Fall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_OUT Rise Time
SDATA_OUT Fall Time
End of Slot 2 to BIT_CLK, SDATA_IN Low
Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT)
Rising Edge of RESET to HI-Z Delay (ATE Test Mode)
Propagation Delay
RESET Rise Time
tRST_LOW
tRST2CLK
tSYNC_HIGH
tSYNC_LOW
tSYNC2CLK
tCLK_PERIOD
tCLK_HIGH
tCLK_LOW
tSYNC_PERIOD
tSETUP
tHOLD
tRISECLK
tFALLCLK
tRISESYNC
tFALLSYNC
tRISEDIN
tFALLDIN
tRISEDOUT
tFALLDOUT
tS2_PDOWN
tSETUP2RST
tOFF
50
80
162.8
36.62
36.62
5
5
2
2
2
2
2
2
2
2
0
15
NOTES
1Guaranteed, not tested.
2Output jitter is directly dependent on crystal input jitter.
Specifications subject to change without notice.
Typ
833
19.5
12.288
81.4
40.69
40.69
48.0
20.8
2.5
4
4
4
4
4
4
4
4
Max Unit
750
44.76
44.76
10
10
10
10
10
10
10
10
10
25
15
50
ns
µs
ns
µs
ns
MHz
ns
ps
ns
ns
kHz
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
REV. 0
–5–
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