AD1881A 查看數據表（PDF） - Analog Devices

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比赛名单

AD1881A

AC’97 SoundMAX® Codec

Analog Devices 

AD1881A

RESET

BIT_CLK

tRST_LOW

tRST2CLK

Figure 1. Cold Reset

SYNC

BIT_CLK

tSYNC_HIGH

tRST2CLK

Figure 2. Warm Reset

BIT_CLK

SYNC

tCLK_LOW

tCLK_HIGH

tCLK_PERIOD

tSYNC_LOW

tSYNC_HIGH

tSYNC_PERIOD

Figure 3. Clock Timing

tSETUP

BIT_CLK

SYNC

SDATA_OUT

tHOLD

Figure 4. Data Setup and Hold

BIT_CLK

tRISECLK

tFALLCLK

SYNC

tRISESYNC

tFALLSYNC

SDATA_IN

tRISEDIN

tFALLDIN

SDATA_OUT

tRISEDOUT

tFALLDOUT

Figure 5. Signal Rise and Fall Time

SYNC SLOT 1 SLOT 2

BIT_CLK

SDATA_OUT

WRITE

TO 0x26

DATA

PR4

DON’T

CARE

tS2_PDOWN

SDATA_IN

NOTE: BIT_CLK NOT TO SCALE

Figure 6. AC Link Low Power Mode Timing

RESET

SDATA_OUT

SDATA_IN, BIT_CLK

tSETUP2RST

HI-Z

tOFF

Figure 7. ATE Test Mode

–6–

REV. 0

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