W83194BR-138 查看數據表（PDF） - Winbond

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W83194BR-138

200MHZ CLOCK FOR SOLANO CHIPSET

Winbond 

W83194BR-138

PRELIMINARY

4.1 Crystal I/O

SYMBOL

Xin

Xout

PIN

I/O

FUNCTION

3

IN Crystal input with internal loading capacitors(36pF)

and feedback resistors.

4

OUT Crystal output at 14.318MHz nominally with internal

loading capacitors(36pF).

4.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs

SYMBOL

PIN

I/O

FUNCTION

CPUCLK [0:1]

45,44

OUT Low skew (< 250ps) clock outputs for host

frequencies such as CPU and Chipset.

PD#/ RESET$

22

I/OD If Mode1*=1, Power Down mode when driven low.

If Mode1*=0, 4ms pulse RESET# (open drain) when

Watch dog timer time out

IOAPIC

47

OUT Clock outputs synchronous with PCI clock and

powered by VddA.

SDRAM_F,

SDRAM[0:7]

31,32,33,35,36 OUT SDRAM clock outputs.

,37,39,40,41

PCICLK0/ *FS0

12

I/O 3.3V 33MHz PCI clock during normal operation.

Latched input for FS0 at initial power up for H/W

selecting the output frequency of CPU, SDRAM and

PCI clocks(Default=1).

PCICLK1/ FS1&

13

I/O Low skew (< 250ps) PCI clock outputs.

Latched input for FS1 at initial power up for H/W

selecting the output frequency of CPU, SDRAM and

PCI clocks(Default=0).

PCICLK2/ Mode1*

15

I/O Low skew (< 250ps) PCI clock outputs.

Latched input for Mode1* pin at initial power up for

the output PD#/RESET# output selection.

PCICLK [ 3:6 ]

16,17,19,20 OUT Low skew (< 250ps) PCI clock outputs.

3V66 [0:2]

7,8,9

OUT 3.3V output clocks for the chipset.

Publication Release Date: May 2000

-3-

Revision 0.37

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