W83194BR-138 查看數據表（PDF） - Winbond

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W83194BR-138

200MHZ CLOCK FOR SOLANO CHIPSET

Winbond 

W83194BR-138

4.3 I2C Control Interface

SYMBOL

PIN

*SDATA

24

*SDCLK

23

PRELIMINARY

I/O

FUNCTION

I/O Serial data of I2C 2-wire control interface with internal

pull-up resistor.

IN Serial clock of I2C 2-wire control interface with

internal pull-up resistor.

4.4 Fixed Frequency Outputs

SYMBOL

PIN

REF0 / *SEL24_48#

1

24_48MHz/FS2&

28

48MHz_0/ FS3*

27

48MHz_1/ FS4*

26

I/O

FUNCTION

I/O 14.318MHz reference clock. This REF output is the

stronger buffer for ISA bus loads.

Latched input for SEL24_48 at initial power up for

H/W selecting the output frequency of 24_48MHz

(Default=1, 24MHz).

I/O 24MHz or 48MHz output clock. Default is 24MHz.

Latched input for FS2 at initial power up for H/W

selecting the output frequency of CPU, SDRAM and

PCI clocks(Default=0).

I/O 48MHz / Latched input for FS3 at initial power up

for H/W selecting the output frequency of CPU,

SDRAM and PCI clocks (Default=1).

I/O 48MHz / Latched input for FS3 at initial power up

for H/W selecting the output frequency of CPU,

SDRAM and PCI clocks (Default=1).

4.5 Power Pins

SYMBOL

VddC,VddA

Vdd48

Vdd3

VddP

VddR

VddS

Vss

PIN

FUNCTION

46,48

Power supply for CPU & IOAPIC, 2.5V or 3.3V.

25

Power supply for 48MHz output,3.3V.

10

Power supply for 3V_66 output, 3.3V.

11,18

Power supply for PCICLK, 3.3V.

2

Power supply for REF0, 3.3V.

30,38

Power supply for SDRAM_F,SDRAM[0:11], nominal

3.3V.

5,6,14,21,29,34,42, Circuit Ground.

43

Publication Release Date: May 2000

-4-

Revision 0.37

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