ETF6122 查看數據表（PDF） - TriQuint Semiconductor

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ETF6122

1 Gigasample/sec, 8-bit Digital-to-Analog Converter

TriQuint Semiconductor 

Figure 7. TQ6122 Data and Control Timing

CLOCK

TDS

DATA

TSS

SELA

TQ6122

TDH

TSH

Symbol

TDS

TDH

TSS

TSH

Description

Data setup time (1)

Data hold time (2)

SELA setup time (1,3)

SELA hold time (2,3)

Typical @ 25 °C

Unit

0

␣ ps

+325

␣ ps

+350

␣ ps

–100

␣ ps

Notes: 1. Setup time is defined to be positive for data or control transitions occurring before the negative-going edge of the clock.

2. Hold time is defined to be positive for data or control transitions occurring after the negative-going edge of the clock.

3. While SELA does not strictly have a setup and hold time, it is convenient to express its allowed transition

region limits in these terms.

For additional information and latest specifications, see our website: www.triquint.com

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