74HC3G34(2018) 查看數據表（PDF） - NXP Semiconductors.
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74HC3G34 Datasheet PDF : 13 Pages
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Nexperia
74HC3G34; 74HCT3G34
Triple buffer gate
VI 90 %
tW
negative
pulse
VM
10 %
0V
tf
VI
positive
pulse
tr
90 %
VM
10 %
0V
tW
VM
tr
tf
VM
VI
G
VCC
VO
DUT
RT
VCC
RL S1
CL
open
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Test data is given in Table 10.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Figure 5. Test circuit for measuring switching times
Table 10. Test data
Type
Input
VI
74HC3G34
GND to VCC
74HCT3G34
GND to 3 V
tr, tf
≤ 6 ns
≤ 6 ns
Load
CL
50 pF
50 pF
RL
1 kΩ
1 kΩ
S1 position
tPHL, tPLH
open
open
74HC_HCT3G34
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 11 June 2018
© Nexperia B.V. 2018. All rights reserved.
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