70P2352-IGT 查看數據表（PDF） - Unspecified

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70P2352-IGT

Dual Channel OC-3/ STM1-E/ E4 LIU

Unspecified 

78P2352

Dual Channel

OC-3/ STM1-E/ E4 LIU

PIN DESCRIPTION

LEGEND

TYPE

A

CIT

DESCRIPTION

Analog Pin

(Tie unused pins to ground)

3-State CMOS Digital Input

CI

CMOS Digital Input

(Tie unused pins to ground)

CIU CMOS Digital Input w/ Pull-up

CID CMOS Digital Input w/ Pull-down

CIS

CMOS Schmitt Trigger Input

(Tie unused pins to ground)

PI

LVPECL-Compatible Differential Input

(Tie unused pins to ground)

TRANSMITTER PINS

TYPE

PO

CO

COZ

OD

S

DESCRIPTION

LVPECL-Compatible Differential Output

(Tie unused pins to supply or leave floating)

CMOS Digital Output

(Leave unused pins floating)

CMOS Tristate Digital Output

(Leave unused pins floating)

Open-drain Digital Output

(Leave unused pins floating)

Supply

G Ground

NAME

PIx0D

PIx1D

PIx2D

PIx3D

PIxCK

PTOxCK

SIxDP

SIxDN

SIxCKP

SIxCKN

CMIxP

CMIxN

TXxCKP

TXxCKN

ECLxP

ECLxN

PIN TYPE DESCRIPTION

31, 66

32, 65

33, 64

34, 63

Transmit (Parallel Mode) Data Input:

CI Four-bit CMOS parallel (nibble) inputs. Data is latched in on the rising edge

(default) of the transmit parallel clock and serialized with the MSB (PIx3D)

transmitted first.

Transmit (Parallel Mode) Clock Input:

30, 67

CIS A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock input that must be

source synchronous with the reference clock supplied at the CKREFP/N pins.

Used only in Slave Parallel Mode and Loop-timing Parallel Mode.

Transmit (Parallel Mode) Clock Output:

35, 62

CO A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock output that is

intended to latch in synchronous parallel data. Active during reset. Used only

in Master Parallel Mode (output disabled in all other transmit modes).

10, 87

11, 86

Transmit (Serial Mode) Data Input:

PI Differential NRZ data input. See Transmitter Operation section for more info

on different clocking/timing modes.

7, 90

8, 89

Transmit (Serial Mode) Clock Input:

PI A 155.52MHz synchronous differential input clock used to clock in the serial

NRZ data. By default, data is clocked in on the rising edge of SIxCKP.

Transmit (Serial Mode) CMI Data Output:

121, 104

A CMI encoded data signal conforming to the relevant ITU-T G.703 pulse

122, 103

A

templates when properly terminated and transformer coupled to 75Ω cable.

Outputs are tri-stated when transmitter is disabled. Active, but undefined

during reset.

124, 101

Transmit (Serial Mode) Clock Output:

125, 100

PO

A 2x line rate LVPECL clock output used to clock out the transmit CMI data.

Used for diagnostics or far end re-timing. Active during reset.

127, 98

128, 97

Transmit (Serial Mode) LVPECL Data Output:

PO Transmit NRZ data outputs used for interfacing with optical transceiver

modules when in Fiber (NRZ) mode.

Page: 16 of 42

2006 Teridian Semiconductor Corporation

Rev. 2.4

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