70P2352-IGT 查看數據表（PDF） - Unspecified

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70P2352-IGT

Dual Channel OC-3/ STM1-E/ E4 LIU

Unspecified 

78P2352

Dual Channel

OC-3/ STM1-E/ E4 LIU

PIN DESCRIPTION (CONTINUED)

REFERENCE AND STATUS PINS

Note: The LOSx, LOLx, and INTxXxB pins are configurable at final test (default open-drain outputs). If CMOS

level outputs are required, please refer to alternate 70Pxxxx ordering numbers at the end of the data sheet.

NAME

CKREFP

CKREFN

LOS1

LOS2

LOL1

LOL2

INTTX1B

INTTX2B

INTRX1B

INTRX2B

PORB

PIN TYPE DESCRIPTION

Reference Clock Input:

A required reference clock input used for clock/data recovery and frequency

synthesizer. Options include :

111

PI/

• 139.264 MHz (E4) or 155.52 MHz (STM1) differential LVPECL clock

110

CI

input at CKREFP/N

• 17.408 MHz (E4), 19.44 MHz (STM1), or 77.78 MHz (STM1) single-

ended CMOS clock input at CKREFP. Tie CKREFN to ground when

unused.

80

OD/ Receive Loss of Signal (active-high):

19

CO See Receiver Loss of Signal description for conditions.

79

OD/ Receive Loss of Lock (active-high):

20

CO

This condition is met when the recovered clock frequency differs from the

reference clock frequency by more than +/- 100ppm.

Transmitter Fault Interrupt Flag (active low):

When a transmitter error event occurs (as defined in the Interrupt Control

88

OD/ Register Description), the INTTXxB pin will change state to indicate an

interrupt. The interrupt is cleared by a read to the STAT Register, an issue

9

CO of a FRSTx FIFO reset pulse (if the FIERRx signal caused the interrupt), or

when the TXLOL register bit transitions from high to low.

Note: The default interrupt condition is a loss of lock in the transmitter CDR.

70

OD/ Receiver Fault Interrupt Flag (active low):

27

CO Reserved for future use.

Power-On Reset (active low):

83

A

See Power-On Reset description on use of this pin.

Page: 18 of 42

2006 Teridian Semiconductor Corporation

Rev. 2.4

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