A6173081S 查看數據表（PDF） - AMIC Technology

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A6173081S

128K X 8 BIT HIGH SPEED CMOS SRAM

AMIC Technology 

Timing Waveforms (continued)

Read Cycle 2(1, 2, 4)

Address

DOUT

tRC

tAA

tOH

Read Cycle 3(1, 3, 4,)

CE

DOUT

tCLZ5

tACE

A6173081 Series

tOH

tCHZ5

Notes: 1. WE is high for Read Cycle.

2. Device is continuously enabled, CE = VIL.

3. Address valid prior to or coincident with CE transition low.

4. OE = VIL.

5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (July, 2000, Version 0.0)

6

AMIC Technology, Inc.

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