GS88218BD-133I 查看數據表（PDF） - Giga Semiconductor

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GS88218BD-133I

512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs

Giga Semiconductor 

GS88218/36BB/D-250/225/200/166/150/133

GS88218/36 BGA Pin Description

Symbol

A0, A1

An

A17, A18

DQA1–DQA9

DQB1–DQB9

DQC1–DQC9

DQD1–DQD9

BA, BB, BC, BD

NC

NC

CK

BW

GW

E1

E3

E2

G

ADV

ADSC, ADSP

ZZ

FT

LBO

ZQ

TMS

TDI

TDO

TCK

MCL

SCD

VDD

VSS

VDDQ

Type

I

I

Description

Address field LSBs and Address Counter Preset Inputs

Address Inputs

Address Inputs

I/O

Data Input and Output pins

I

Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

—

No Connect

—

No Connect

I

Clock Input Signal; active high

I

Byte Write—Writes all enabled bytes; active low

I

Global Write Enable—Writes all bytes; active low

I

Chip Enable; active low

I

Chip Enable; active low

I

Chip Enable; active high

I

Output Enable; active low

I

Burst address counter advance enable; active l0w

I

Address Strobe (Processor, Cache Controller); active low

I

Sleep mode control; active high

I

Flow Through or Pipeline mode; active low

I

Linear Burst Order mode; active low

I

FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low

Drive])

I

Scan Test Mode Select

I

Scan Test Data In

O

Scan Test Data Out

I

Scan Test Clock

—

Must Connect Low

—

Single Cycle Deselect/Dual Cyle Deselect Mode Control

I

Core power supply

I

I/O and Core Ground

I

Output driver power supply

Rev: 1.00b 12/2002

6/33

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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