GS88218BD-133I 查看數據表（PDF） - Giga Semiconductor

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GS88218BD-133I

512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs

Giga Semiconductor 

GS88218/36B (PE = 0) Block Diagram

A0–An

LBO

ADV

CK

ADSC

ADSP

GW

BW

BA

Register

DQ

A0

A1

A0

D0

Q0 A1

D1

Q1

Counter

Load

Register

DQ

Register

DQ

BB

Register

DQ

BC

Register

DQ

BD

Register

DQ

Register

E1

DQ

Register

DQ

FT

G

Power Down

ZZ

Control

Note: Only x36 version shown for simplicity.

SCD

GS88218/36BB/D-250/225/200/166/150/133

A

Memory

Array

Q

36

D

36

4

4

36

36

36

DQx1–DQx9

36

36

4

32

Parity

Encode

4

Parity

Compare

NC

NC

Rev: 1.00b 12/2002

7/33

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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