AD5044 查看數據表（PDF） - Analog Devices
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AD5044 Datasheet PDF : 28 Pages
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AD5024/AD5044/AD5064
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LDAC 1
SYNC 2
VDD 3
VREFB 4
VREFA 5
VOUTA 6
VOUTC 7
POR 8
AD5024/
AD5044/
AD5064
TOP VIEW
(Not to Scale)
16 SCLK
15 DIN
14 GND
13 VOUTB
12 VOUTD
11 VREFD
10 CLR
9 VREFC
Figure 3. 16-Lead TSSOP (RU-16) Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
LDAC
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This
allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low.
2
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on
the falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge
of SYNC acts as an interrupt and the write sequence is ignored by the device.
3
VDD
Power Supply Input. These parts can be operated from 4.5 V to 5.5 V, and the supply should be decoupled
with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
4
VREFB
5
VREFA
6
VOUTA
7
VOUTC
DAC B Reference Input. This is the reference voltage input pin for DAC B.
DAC A Reference Input. This is the reference voltage input pin for DAC A.
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
8
POR
Power-On Reset. Tying this pin to GND powers up the part to 0 V. Tying this pin to VDD powers up the
part to midscale.
9
VREFC
10
CLR
DAC C Reference Input .This is the reference voltage input pin for DAC C.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
ignored. When CLR is activated, the input register and the DAC register are updated with the data
contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
11
VREFD
DAC D Reference Input .This is the reference voltage input pin for DAC D.
12
VOUTD
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
13
VOUTB
14
GND
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
15
DIN
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
16
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates of up to 50 MHz.
Rev. 0 | Page 8 of 28
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