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AD5426 查看數據表(PDF) - Analog Devices

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AD5426 Datasheet PDF : 24 Pages
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AD5426/AD5432/AD5443–SPECIFICATIONS1
(VDD = 3 V to 5.5 V, VREF = 10 V, IOUTx = O V. All specifications TMIN to TMAX, unless otherwise noted. DC performance measured with OP177, AC
performance with AD8038, unless otherwise noted.)
Parameter
Min
Typ Max Unit
Conditions
STATIC PERFORMANCE
AD5426
Resolution
Relative Accuracy
Differential Nonlinearity
AD5432
Resolution
Relative Accuracy
Differential Nonlinearity
AD5443
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Error Temperature Coefficient2
Output Leakage Current
REFERENCE INPUT2
Reference Input Range
VREF Input Resistance
RFB Resistance
Input Capacitance
Code All 0s
Code All 1s
DIGITAL INPUTS/OUTPUT2
Input High Voltage, VIH
Input Low Voltage, VIL
Input Leakage Current, IIL
Input Capacitance
VDD = 4.5 V to 5.5 V
Output Low Voltage, VOL
Output High Voltage, VOH
VDD = 3 V to 3.6 V
Output Low Voltage, VOL
Output High Voltage, VOH
DYNAMIC PERFORMANCE2
Reference Multiplying Bandwidth
Output Voltage Settling Time
AD5426
AD5432
AD5443
Digital Delay
10% to 90% Rise/Fall Time
Digital-to-Analog Glitch Impulse
Multiplying Feedthrough Error
Output Capacitance
IOUT2
IOUT1
Digital Feedthrough
Total Harmonic Distortion
Digital THD Clock = 1 MHz
50 kHz fOUT
Output Noise Spectral Density
8
Bits
± 0.25 LSB
± 0.5 LSB
Guaranteed monotonic
10
Bits
± 0.5 LSB
± 1 LSB
Guaranteed monotonic
12
Bits
± 1 LSB
–1/+2 LSB
Guaranteed monotonic
± 10 mV
±5
ppm FSR/°C
± 5 nA
± 25 nA
Data = 0x0000, TA = 25°C, IOUT
Data = 0x0000, IOUT
± 10
V
8
10 12
k
8
10 12
k
36
pF
58
pF
Input resistance TC = –50 ppm/°C
Input resistance TC = –50 ppm/°C
1.7
V
0.6 V
2
A
4
10
pF
VDD – 1
VDD – 0.5
0.4 V
V
0.4 V
V
10
50 100
55 110
90 160
40 75
15 30
2
70
48
22 25
10 12
12 17
25 30
0.1
–81
73
25
MHz
ns
ns
ns
ns
ns
nV-s
dB
dB
pF
pF
pF
pF
nV-s
dB
dB
nV/Hz
ISINK = 200 A
ISOURCE = 200 A
ISINK = 200 A
ISOURCE = 200 A
VREF = ± 3.5 V; DAC loaded all 1s
VREF = 10 V; RLOAD = 100 , CLOAD = 15 pF
Measured to ±16 mV of full scale
Measured to ± 4 mV of full scale
Measured to ± 1 mV of full scale
Interface Delay Time
Rise and fall time, VREF = 10 V, RLOAD = 100
1 LSB change around major carry, VREF = 0 V
DAC latch loaded with all 0s. VREF = ±3.5 V
1 MHz
10 MHz
All 0s loaded
All 1s loaded
All 0s loaded
All 1s loaded
Feedthrough to DAC output with SYNC high and
alternate loading of all 0s and all 1s
VREF = 3.5 V pk-pk; all 1s loaded, f = 1 kHz
@ 1 kHz
–2–
REV. 0

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