AD5428 查看數據表（PDF） - Analog Devices
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AD5428 Datasheet PDF : 33 Pages
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Data Sheet
AD5428/AD5440/AD5447
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
Write Mode
t1
t2
t3
t4
t5
t6
t7
t8
t9
Data Readback Mode
t10
t11
t12
t13
Update Rate
Limit at TMIN, TMAX
0
0
10
10
0
6
0
5
7
0
0
5
25
5
10
21.3
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns typ
ns typ
ns max
ns typ
ns max
MSPS
Conditions/Comments
R/W to CS setup time
R/W to CS hold time
CS low time
Address setup time
Address hold time
Data setup time
Data hold time
R/W high to CS low
CS min high time
Address setup time
Address hold time
Data access time
Bus relinquish time
Consists of CS min high time, CS low time, and output
voltage settling time
1 Guaranteed by design and characterization, not subject to production test.
R/W
CS
DACA/DACB
DATA
t1
t2
t8
t2
t9
t3
t5
t4
t10
t11
t8
t7
DATA VALID
t12
t13
DATA VALID
Figure 2. Timing Diagram
TO OUTPUT
PIN
200μA
CL
50pF
200μA
IOL
VOH (MIN) + VOL (MAX)
2
IOH
Figure 3. Load Circuit for Data Output Timing Specifications
Rev. C | Page 5 of 32
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