Preliminary Technical Information
TIMING CHARACTERISTICS
Parameter
t90
t91
t92
t93
t94
t95
Comment (see Figure 21)
VSCLK period
VSFS setup time before VSCLK low
VSFS hold time after VSCLK low
VSDI setup time before VSCLK low
VSDI hold time after VSCLK low
VSDO delay after VSCLK high
AD6426
EVBC Interface VSPORT
Min
Typ
Max Units
76.9
ns
4
ns
7
ns
4
ns
7
ns
0
15
ns
VSCLK (I)
VSFS (I)
VSDI (I)
VSDO (O)
t90
t91
t92
t93
t94
D15 D14
t95
D15
D14
D13
Figure 21. EVBC Interface VSPORT Timing
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
- 41 -
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