AD6426 查看數據表（PDF） - Analog Devices
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AD6426 Datasheet PDF : 50 Pages
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AD6426 Data Sheet Change Summary
Number
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Date
1/15/98
1/15/98
1/15/98
1/15/96
1/15/98
1/15/98
1/15/98
1/15/98
1/15/98
1/15/98
1/15/98
1/15/98
2/16/98
2/16/98
2/16/98
2/16/98
2/16/98
2/26/98
2/26/98
2/26/98
2/26/98
2/26/98
2/26/98
2/27/98
2/27/98
2/27/98
3/9/98
3/9/98
3/9/98
AD6426 Preliminary Revision 1.0
(Changes from Revision 0.1)
Description of Change
Dallas I/F added to Feature list.
Dallas I/F enable bit polarity changed from logic 1 to 0.
Dual Band control section added describing BANDSELECT and DCSSEL signals.
Serial Display Interface Timing Characteristics and Diagram added as Figure 23.
General Description: F7.2 data services deleted, this is not supported on the EGSMP.
General Description: AD6421/25 interfaces to the EGSMP.
Serial Display Reset signal removed from Figure 2.
Display driver chip reset input is connected to the AD6425 VBC Reset Input and both are driven by
the AD6426 VBC reset output.
Pin Functionality: VBCRESET added note, also used for Display Reset.
Pin Functionality: GPIO1 added note, alternate function DCS_ON.
CC Control Registers: Interrupt counter (Addr. 48) changed from 7 to 8 bits.
SIM Interface timing characteristics deleted - SIM signals are completely asynchronous with respect
to SIMCLK.
Plastic Ball Grid Array (PBGA) Package pinout and outline drawing added.
EVBC and radio Interface block diagram in Figure 6 updated with dual band control signals.
VCLKIN, Clock Input Voltage for ac-coupled sine wave input changed from 100 mVPP to 250 mVPP.
Added scan registers USCRX (O), USCRXEN (B), and VSDOEN (T)
Corrected output polarity in Notes to active-low (0=output).
Added H8 Control registers and register contents in Tables 3 and 4.
Buffered UART Register Contents added in Table 5.
IIH, IIL Input Current spec min -10, max 10 µA added.
IIH, IIL Input Current spec min -10, max 10 µA added.
IOZL, Low Level Output 3-State Leakage Current min 10, max 10 µA IOZH, High Level Output 3-State
Leakage Current min 10, max 10 µA.
Absolute Max ratings broken out separately for PBGA package.
Control Processor Data setup time changed from 10 to 68 ns.
Radio interface section: a reference to the TTP/Hitachi radios added “AD6426 Radio Interface
supports radio architectures based on Siemens, Philips, and TTP/Hitachi RF chipsets”.
Pin Functionality: OSC13MON pin moved from RTC section to general section.
Memory interface timing diagram replaced with one used in 6422 data sheet.
CC register 46 bits 4-7 SIMCLOCK Polarity, SIMCLOCK off. SIMCLOCK Control, STBYCLKON
removed no longer used on 6426.
CC registers 80-87 slow clocking control removed from Table 1 & 2 per TTP’s request.
Peripheral registers 83, 106-109 removed from Table 3 & 4 per TTP’s request.
All Buffered UART registers removed per TTP’s request.
June 10, 1998
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